103 lines
2.2 KiB
Verilog
103 lines
2.2 KiB
Verilog
//
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// Copyright 2012 Ettus Research LLC
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// Copyright 2018 Ettus Research, a National Instruments Company
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// Copyright 2020 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Description: 32 word FIFO with AXI4-Stream interface.
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//
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// NOTE: This module uses the SRLC32E primitive explicitly and as such can
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// only be used with Xilinx technology.
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//
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module axi_fifo_short #(
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parameter WIDTH = 32
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) (
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input clk,
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input reset,
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input clear,
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input [WIDTH-1:0] i_tdata,
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input i_tvalid,
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output i_tready,
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output [WIDTH-1:0] o_tdata,
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output o_tvalid,
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input o_tready,
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output reg [5:0] space,
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output reg [5:0] occupied
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);
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reg full = 1'b0, empty = 1'b1;
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wire write = i_tvalid & i_tready;
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wire read = o_tready & o_tvalid;
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assign i_tready = ~full;
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assign o_tvalid = ~empty;
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reg [4:0] a;
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genvar i;
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generate
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for (i=0;i<WIDTH;i=i+1) begin : gen_srlc32e
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SRLC32E srlc32e(
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.Q(o_tdata[i]), .Q31(),
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.A(a),
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.CE(write),.CLK(clk),.D(i_tdata[i])
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);
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end
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endgenerate
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always @(posedge clk) begin
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if(reset) begin
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a <= 0;
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empty <= 1;
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full <= 0;
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end
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else if(clear) begin
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a <= 0;
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empty <= 1;
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full<= 0;
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end
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else if(read & ~write) begin
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full <= 0;
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if(a==0)
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empty <= 1;
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else
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a <= a - 1;
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end
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else if(write & ~read) begin
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empty <= 0;
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if(~empty)
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a <= a + 1;
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if(a == 30)
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full <= 1;
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end
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end
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// NOTE: Will fail if you write into a full FIFO or read from an empty one
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always @(posedge clk) begin
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if(reset)
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space <= 6'd32;
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else if(clear)
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space <= 6'd32;
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else if(read & ~write)
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space <= space + 6'd1;
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else if(write & ~read)
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space <= space - 6'd1;
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end
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always @(posedge clk) begin
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if(reset)
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occupied <= 6'd0;
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else if(clear)
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occupied <= 6'd0;
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else if(read & ~write)
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occupied <= occupied - 6'd1;
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else if(write & ~read)
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occupied <= occupied + 6'd1;
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end
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endmodule // axi_fifo_short
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