144 lines
3.6 KiB
PHP
144 lines
3.6 KiB
PHP
#
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# Copyright 2018-2019 Ettus Research, a National Instruments Brand
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#
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##################################################
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# Project Setup
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##################################################
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# TOP_MODULE = <Input arg>
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# NAME = <Input arg>
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# PART_ID = <Input arg>
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# ARCH = <Input arg>
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##################################################
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# Include other makefiles
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##################################################
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BASE_DIR = $(abspath ..)
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IP_DIR = $(abspath ./ip)
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include $(BASE_DIR)/../tools/make/viv_design_builder.mak
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include $(IP_DIR)/Makefile.inc
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include ../n3xx/coregen_dsp/Makefile.srcs
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include $(LIB_DIR)/ip/Makefile.inc
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include $(LIB_DIR)/hls/Makefile.inc
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include $(LIB_DIR)/control/Makefile.srcs
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include $(LIB_DIR)/fifo/Makefile.srcs
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include $(LIB_DIR)/simple_gemac/Makefile.srcs
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include $(LIB_DIR)/axi/Makefile.srcs
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include $(LIB_DIR)/timing/Makefile.srcs
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include $(LIB_DIR)/packet_proc/Makefile.srcs
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include $(LIB_DIR)/xge/Makefile.srcs
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include $(LIB_DIR)/xge_interface/Makefile.srcs
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include $(LIB_DIR)/dsp/Makefile.srcs
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include $(LIB_DIR)/io_cap_gen/Makefile.srcs
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include $(LIB_DIR)/rfnoc/Makefile.srcs
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include $(LIB_DIR)/axi4s_sv/Makefile.srcs
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include $(LIB_DIR)/rfnoc/xport_sv/Makefile.srcs
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# If out-of-tree modules want to be compiled into this image, then they need to
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# pass in the RFNOC_OOT_MAKEFILE_SRCS as a list of Makefile.srcs files.
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# Those files need to amend the RFNOC_OOT_SRCS variable with a list of actual
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# source files.
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-include $(RFNOC_OOT_MAKEFILE_SRCS)
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ifdef BUILD_DIR
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include $(BUILD_DIR)/Makefile.inc
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endif
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##################################################
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# Sources
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##################################################
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TOP_SRCS = \
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e320.v \
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e320_core.v \
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e320_clocking.v \
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e320_sfp_wrapper.v \
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e320_mgt_io_core.v \
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$(IMAGE_CORE)
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MB_XDC = \
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mb_pins.xdc \
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mb_timing.xdc
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ifdef BUILD_10G
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MB_XDC += $(abspath e320_10ge.xdc)
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endif
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ifdef BUILD_1G
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MB_XDC += $(abspath e320_1ge.xdc)
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endif
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ifdef BUILD_AURORA
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MB_XDC += $(abspath e320_aurora.xdc)
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endif
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ifdef SFP_10GBE
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MB_XDC += $(abspath e320_10ge_port0.xdc)
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endif
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ifndef NO_DRAM_FIFOS
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DRAM_SRCS = $(IP_DRAM_XCI_SRCS) $(abspath e320_dram.xdc)
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else
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DRAM_SRCS =
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endif
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DESIGN_SRCS = $(abspath \
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$(CONTROL_LIB_SRCS) \
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$(IP_XCI_SRCS) \
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$(TEN_GIGE_PHY_SRCS) \
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$(XGE_SRCS) \
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$(XGE_INTERFACE_SRCS) \
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$(PACKET_PROC_SRCS) \
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$(AXI_SRCS) \
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$(AXI4S_SV_SRCS) \
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$(FIFO_SRCS) \
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$(ONE_GIGE_PHY_SRCS) \
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$(SIMPLE_GEMAC_SRCS) \
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$(AURORA_PHY_SRCS) \
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$(BD_SRCS) \
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$(TIMING_SRCS) \
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$(CAT_CAP_GEN_SRCS) \
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$(DRAM_SRCS) \
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$(COREGEN_DSP_SRCS) \
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$(DSP_SRCS) \
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$(LIB_IP_XCI_SRCS) \
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$(LIB_HLS_IP_SRCS) \
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$(EXTRAM_SRCS) \
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$(CAP_GEN_GENERIC_SRCS) \
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$(RFNOC_FRAMEWORK_SRCS) \
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$(RFNOC_SRCS) \
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$(RFNOC_OOT_SRCS) \
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$(RFNOC_XPORT_SV_SRCS) \
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$(RFNOC_IMAGE_CORE_SRCS) \
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$(TOP_SRCS) \
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$(MB_XDC) \
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)
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IMAGE_CORE_HEADER_DEF="RFNOC_IMAGE_CORE_HDR=$(BUILD_DIR)/rfnoc_image_core.vh"
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##################################################
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# Dependency Targets
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##################################################
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.SECONDEXPANSION:
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VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(IMAGE_CORE_HEADER_DEF) $(RFNOC_IMAGE_CORE_DEFS)
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# DESIGN_SRCS and VERILOG_DEFS must be defined
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bin: .prereqs
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@echo "Build directory:: $(BUILD_DIR)"
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@echo "Printing MB_XDC:: $(MB_XDC)"
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@echo "Printing VERILOG_DEFS:: $(VERILOG_DEFS)"
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$(call BUILD_VIVADO_DESIGN,$(abspath ./build_e320.tcl),$(TOP_MODULE),$(ARCH),$(PART_ID))
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synth: .prereqs
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$(call BUILD_VIVADO_DESIGN,$(TOOLS_DIR)/scripts/viv_synth.tcl,$(TOP_MODULE),$(ARCH),$(PART_ID))
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rtl: .prereqs
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$(call CHECK_VIVADO_DESIGN,$(TOOLS_DIR)/scripts/viv_check_syntax.tcl,$(TOP_MODULE),$(ARCH),$(PART_ID))
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viv_ip: .prereqs $$(DESIGN_SRCS) ip
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@echo "IP build for $(NAME) DONE . . ."
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.PHONY: bin synth rtl viv_ip
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