miegl/b210-k7-fpga
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b210-k7-fpga/tools/scripts
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Max Köhler 067f150b75 fpga: tools: mark hash dirty with staged changes 
Original-commit: d635ee91fb34fa1fbb0c70a23337f4ea5a05cc1f
2025-01-29 11:37:22 +01:00
..
check_config.json
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
dmd_design_build.tcl
fpga: tools: Lattice build flow clean-up
2022-08-03 14:28:21 -05:00
git-hash.sh
fpga: tools: mark hash dirty with staged changes
2025-01-29 11:37:22 +01:00
ise_jtag_program.sh
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
launch_modelsim.sh
fpga: tools: Add do file for ModelSim
2024-10-08 18:15:52 -05:00
launch_vivado.py
fpga: tools: Spruce up launch_vivado.py
2023-12-13 17:28:09 -06:00
launch_vivado.sh
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
launch_vlint.sh
fpga: tools: Fix HLS IP builder for Vivado 2021.1
2022-08-25 13:55:30 -05:00
modelsim.do
fpga: tools: Add do file for ModelSim
2024-10-08 18:15:52 -05:00
setupenv_base.sh
fpga: tools: Fix HLS IP builder for Vivado 2021.1
2022-08-25 13:55:30 -05:00
shared-ip-loc-manage.sh
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
viv_check_syntax.tcl
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
viv_gen_ip_makefile.py
fpga: Remove Python2 support from build system
2021-01-04 13:28:36 -06:00
viv_gen_part_id.py
fpga: Remove Python2 support from build system
2021-01-04 13:28:36 -06:00
viv_generate_bd.tcl
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
viv_generate_hls_ip.tcl
fpga: hls: Add version to generated HLS IP
2022-01-13 14:33:59 -06:00
viv_generate_ip.tcl
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
viv_generate_patch_ip.tcl
fpga: tools: Add ability to patch IP during generation
2021-06-03 10:22:04 -05:00
viv_hardware_utils.tcl
fpga: Fix Vivado version check in viv_hardware_utils
2022-09-08 11:53:44 -05:00
viv_ip_retarget_subcores.py
mpm/fpga: x4xx: Major updates in preparation for future devices
2023-05-23 09:06:17 +02:00
viv_ip_utils.tcl
fpga: tools: Fix VHDL and Verilog types in modify_bdtcl
2024-05-18 21:29:35 -05:00
viv_ip_xci_editor.py
fpga: tools: Allow IP renaming with viv_ip_xci_editor.py
2022-08-25 13:55:30 -05:00
viv_secure_synth.tcl
fpga: x400: Add netlist make flow
2024-06-11 10:20:07 +02:00
viv_sim_project.tcl
fpga: tools: Add UHD_FPGA_DIR definition to synthesis
2021-09-08 08:36:05 -05:00
viv_strategies.tcl
fpga: x4xx: add option for incremental Vivado build
2024-03-12 16:03:23 -05:00
viv_synth.tcl
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
viv_utils.tcl
fpga: tools: Force write when saving Vivado project file
2024-06-11 10:20:08 +02:00
xil_bitfile_parser.py
fpga: Fix Xilinx bitfile parser for Python 3
2021-08-24 09:45:36 -05:00