Wade Fife cfb4ba7f0b fpga: tools: Add ability to patch IP during generation ...

This adds the ability to call BUILD_VIVADO_IP, as before, followed by
REBUILD_VIVADO_IP_WITH_PATCH to patch a file generated by the IP and
then rebuild the IP with the patched file.


Original-commit: 78315eca698333ad4dc32818e24c7bf6a740c0cb

2021-06-03 10:22:04 -05:00

..

viv_design_builder.mak

fpga: Remove Python2 support from build system

2021-01-04 13:28:36 -06:00

viv_hls_ip_builder.mak

fpga: tools: Add contents of directories for HDL source

2020-05-26 13:36:55 -05:00

viv_ip_builder.mak

fpga: tools: Add ability to patch IP during generation

2021-06-03 10:22:04 -05:00

viv_preamble.mak

fpga: Remove Python2 support from build system

2021-01-04 13:28:36 -06:00

viv_sim_preamble.mak

fpga: tools: Add modelsim to make sim targets

2020-03-20 10:34:59 -05:00

viv_simulator.mak

fpga: tools: Allow multiple top modules with ModelSim

2020-06-11 09:53:00 -05:00