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b210-k7-fpga/lib/rfnoc/utils
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Wade Fife 3bc803026b fpga: lib: Pipeline ctrlport_timer 
This pipelines ctrlport_timer to eliminate the long combinational path
caused by the time comparisons. This change also removes the
PRECISION_BITS parameter and converts it to a signal named
time_ignore_bits.


Original-commit: c6035320215f270d7658cfb6195a96a0b84d6aa7
2021-06-03 11:26:54 -05:00
..
axis_ctrlport_reg.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
chdr_pad_packet.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
chdr_trim_payload.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
context_builder.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
context_handler_sync.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
context_parser.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
ctrlport_clk_cross.v
fpga: lib: add handshake to replace FIFO for ctrlport CDC
2020-08-13 07:46:14 -05:00
ctrlport_combiner.v
fpga: rfnoc: ctrport_combiner with deterministic latency for PRIORITY=1
2020-04-01 11:02:16 -05:00
ctrlport_decoder_param.v
fpga: lib: Modify for loop to Verilog 2001 syntax
2020-03-09 13:40:17 -05:00
ctrlport_decoder.v
fpga: lib: modify ctrlport decoder to Verilog 2001 compatible syntax
2020-07-10 15:12:55 -05:00
ctrlport_gate.v
fpga: rfnoc: Add gate to dynamically enable control-port interfaces
2020-04-01 11:02:16 -05:00
ctrlport_reg_ro.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
ctrlport_reg_rw.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
ctrlport_resp_combine.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
ctrlport_splitter.v
fpga: utils: Optimize ctrlport_splitter for NUM_SLAVES = 1
2020-05-12 13:46:28 -05:00
ctrlport_terminator.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
ctrlport_timer.v
fpga: lib: Pipeline ctrlport_timer
2021-06-03 11:26:54 -05:00
ctrlport_to_settings_bus.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
Makefile.srcs
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2020-01-28 09:35:36 -08:00
noc_shell_generic_ctrlport_pyld_chdr.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
timekeeper.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00