miegl/b210-k7-fpga
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b210-k7-fpga/top/n3xx/ip/axi_intercon_4x64_256_bd
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Wade Fife bd5d539bc2 fpga: n3xx: Update AXI interconnect address range 
This change allows the entire 2 GiB address space to be accessed on
each memory port.


Original-commit: c6bb9924e56664ccb337694f8ef485ba8245edfd
2020-08-28 15:07:38 -05:00
..
axi_intercon_4x64_256_bd_wrapper.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_intercon_4x64_256_bd.bd
fpga: n3xx: Update AXI interconnect address range
2020-08-28 15:07:38 -05:00
axi_intercon_4x64_256_bd.bxml
fpga: n3xx: Update AXI interconnect address range
2020-08-28 15:07:38 -05:00
Makefile.inc
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00