Wade Fife 307ba63f99 fpga: lib: Fix trailing bytes in eth_ipv4_chdr_adapter ...

On the CPU to Ethernet path (c2e) in some configurations the trailing
bytes length was not being properly set in TUSER. This can lead to
extra bytes being added onto packets. Most of the time this is fine,
since the extra bytes would be ignored by the underlying protocols.
But when the packet was near the MTU size, it could lead to an
oversized packet that would get dropped by the network or host
computer.


Original-commit: 00d9a228f58b384798f0a1346fbab8f40b017a9c

2025-03-03 09:02:29 -06:00

..

eth_interface_tb

fpga: lib: Add ZPU support to SV transport adapter

2023-01-10 14:18:59 -08:00

chdr_xport_adapter.sv

fpga: lib: Add advanced features to IPv4 SV transport adapter

2022-08-29 17:01:45 -05:00

eth_constants.vh

fpga: lib: Add width agnostic version of Ethernet Interface

2020-06-30 10:29:35 -05:00

eth_ipv4_add_udp.sv

fpga: lib: Add support for length in tuser in eth_ipv4_add_udp

2022-08-29 17:01:45 -05:00

eth_ipv4_chdr_adapter_wrapper.sv

fpga: lib: Add verilog-compatible wrapper for eth_ipv4_chdr_adapter

2023-01-10 14:18:59 -08:00

eth_ipv4_chdr_adapter.sv

fpga: lib: Fix trailing bytes in eth_ipv4_chdr_adapter

2025-03-03 09:02:29 -06:00

eth_ipv4_chdr_dispatch.sv

fpga: lib: add register stage in ipv4 chdr adapter

2025-02-05 09:14:26 -06:00

eth_ipv4_interface_wrapper.sv

fpga: lib: Enable TUSER in eth_ipv4_interface_wrapper

2025-03-03 09:02:29 -06:00

eth_ipv4_interface.sv

fpga: x4xx: Replace Ethernet transport adapter

2024-06-11 10:20:07 +02:00

eth_ipv4_internal.sv

fpga: lib: Fix Vivado warnings

2023-06-09 09:01:04 -05:00

eth_regs.vh

fpga: lib: Add advanced features to IPv4 SV transport adapter

2022-08-29 17:01:45 -05:00

Makefile.srcs

fpga: lib: Add verilog-compatible wrapper for eth_ipv4_chdr_adapter

2023-01-10 14:18:59 -08:00