198 lines
5.6 KiB
PHP
198 lines
5.6 KiB
PHP
#
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# Copyright 2021 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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##################################################
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# Project Setup
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##################################################
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# TOP_MODULE = <Input arg>
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# NAME = <Input arg>
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# PART_ID = <Input arg>
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# ARCH = <Input arg>
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##################################################
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# Include other makefiles
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##################################################
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BASE_DIR = $(abspath ..)
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IP_DIR = $(abspath ./ip)
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include $(BASE_DIR)/../tools/make/viv_design_builder.mak
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# Include IP directory
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include $(IP_DIR)/Makefile.inc
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# Include any LIB dependencies
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include coregen_dsp/Makefile.srcs
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include $(LIB_DIR)/control/Makefile.srcs
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include $(LIB_DIR)/fifo/Makefile.srcs
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include $(LIB_DIR)/xge/Makefile.srcs
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include $(LIB_DIR)/xge_interface/Makefile.srcs
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include $(LIB_DIR)/axi/Makefile.srcs
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include $(LIB_DIR)/packet_proc/Makefile.srcs
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include $(LIB_DIR)/dsp/Makefile.srcs
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include $(LIB_DIR)/ip/Makefile.inc
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include $(LIB_DIR)/rfnoc/Makefile.srcs
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include $(LIB_DIR)/wb_spi/Makefile.srcs
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include $(LIB_DIR)/wishbone/Makefile.srcs
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include $(LIB_DIR)/axi4_sv/Makefile.srcs
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include $(LIB_DIR)/axi4s_sv/Makefile.srcs
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include $(LIB_DIR)/axi4lite_sv/Makefile.srcs
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include $(LIB_DIR)/rfnoc/xport_sv/Makefile.srcs
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# If out-of-tree modules want to be compiled into this image, then they need to
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# pass in the RFNOC_OOT_MAKEFILE_SRCS as a list of Makefile.srcs files.
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# Those files need to amend the RFNOC_OOT_SRCS variable with a list of actual
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# source files.
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-include $(RFNOC_OOT_MAKEFILE_SRCS)
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# Now include everything that falls out of the image builder
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ifdef BUILD_DIR
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include $(BUILD_DIR)/Makefile.inc
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endif
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##################################################
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# Sources
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##################################################
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TOP_SRCS = \
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x4xx.sv \
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x4xx_core.v \
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x4xx_core_common.v \
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x4xx_global_regs.v \
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x4xx_versioning_regs.v \
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x4xx_dio.v \
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x4xx_gpio_atr.v \
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x4xx_gpio_spi.v \
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x4xx_dram.v \
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ctrlport_spi_master.v \
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cpld_interface.v \
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cpld_interface_regs.v \
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qsfp_led_controller.v \
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rfdc_timing_control.v \
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x4xx_pps_sync.v \
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../../lib/timing/pps_generator.v \
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dboards/ctrlport_byte_serializer.v \
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dboards/ctrlport_clk_crossing_derived.v \
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dboards/db_gpio_reordering.v \
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ipass_present_controller.v
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ifdef X410
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TOP_SRCS += \
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rf/100m/rf_core_100m.v \
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rf/200m/rf_core_200m.v \
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rf/200m/rf_down_4to2.v \
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rf/200m/rf_up_2to4.v \
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rf/400m/rf_core_400m.v \
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rf/x410/x410_rf_reset_controller.vhd \
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dboards/zbx/db_gpio_interface.v
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endif
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ifdef X440
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TOP_SRCS += \
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rf/100m/rf_core_100m.v \
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rf/full/rf_core_full.sv \
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rf/common/adc_iq_repacker.v \
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rf/x440/x440_rf_reset_controller.vhd \
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dboards/fbx/db_gpio_interface.v \
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dboards/fbx/ctrlport_to_i2c_sync_ctrl.v \
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dboards/fbx/led_atr_control.v \
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dboards/fbx/clock_en_control.v \
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dboards/fbx/rf_atr_control.v
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endif
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ifdef X410
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MB_XDC += \
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constraints/timing/x410_clocks.xdc
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endif
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ifdef X440
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ifeq ($(RF_BW), 400)
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MB_XDC += \
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constraints/timing/x440_clocks_400.xdc
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endif
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ifeq ($(RF_BW), 1600)
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MB_XDC += \
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constraints/timing/x440_clocks_1600.xdc
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endif
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MB_XDC += \
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constraints/timing/x440_clocks.xdc
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endif
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MB_XDC += \
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constraints/pins/common.xdc \
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constraints/timing/shared_constants.sdc \
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constraints/timing/common.xdc \
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constraints/pins/dram.xdc \
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constraints/timing/dram.xdc
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ifdef X410
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MB_XDC += \
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constraints/pins/rfdc_2x2.xdc \
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constraints/pins/x410/db_gpio.xdc \
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constraints/timing/x410.xdc
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endif
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ifdef X440
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MB_XDC += \
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constraints/pins/rfdc_4x4.xdc \
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constraints/pins/x440/db_gpio.xdc \
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constraints/timing/x440.xdc
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endif
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MB_XDC += $(RFNOC_XDC_SRCS)
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DESIGN_SRCS = $(abspath $(MB_XDC))
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# The XDC files must be read in a specific order, motherboard first and then daughterboard.
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# Outside of that, all the other sources can be read in any order desired.
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DESIGN_SRCS += $(abspath \
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$(AXI4_SV_SRCS) $(AXI4S_SV_SRCS) $(AXI4LITE_SV_SRCS) $(TOP_SRCS) \
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$(AXI_SRCS) $(FIFO_SRCS) \
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$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
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$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(COREGEN_DSP_SRCS) \
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$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) $(WISHBONE_SRCS) \
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$(XGE_SRCS) $(XGE_INTERFACE_SRCS) $(AURORA_PHY_SRCS) \
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$(XGE_PCS_PMA_SRCS) \
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$(PACKET_PROC_SRCS) $(VITA_SRCS) $(DSP_SRCS) $(DRAM_SRCS) \
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$(RADIO_SRCS) $(CAP_GEN_GENERIC_SRCS) $(IP_XCI_SRCS) $(BD_SRCS) \
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$(RFNOC_SRCS) $(RFNOC_OOT_SRCS) $(LIB_IP_XCI_SRCS) $(LIB_HLS_IP_SRCS) $(LIBCOREGEN_SRCS) \
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$(DB_COMMON_SRCS) $(RFNOC_FRAMEWORK_SRCS) \
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$(WB_SPI_SRCS) $(RFNOC_XPORT_SV_SRCS) \
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$(RFNOC_IMAGE_CORE_SRCS) \
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)
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# Pass the image core header files required by RFNoC
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# to Vivado as Verilog definitions.
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IMAGE_CORE_HEADER_DEF="RFNOC_IMAGE_CORE_HDR=$(BUILD_DIR)/rfnoc_image_core.vh"
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##################################################
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# Dependency Targets
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##################################################
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.SECONDEXPANSION:
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VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(IMAGE_CORE_HEADER_DEF) $(RFNOC_IMAGE_CORE_DEFS)
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show-var:
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@echo "IP_BUILD_DIR: $(IP_BUILD_DIR)"
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# DESIGN_SRCS and VERILOG_DEFS must be defined
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bin: .prereqs
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@echo "Build directory:: $(BUILD_DIR)"
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@echo "Printing MB_XDC:: $(MB_XDC)"
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@echo "Printing VERILOG_DEFS:: $(VERILOG_DEFS)"
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$(call BUILD_VIVADO_DESIGN,$(abspath ./build_x4xx.tcl),$(TOP_MODULE),$(ARCH),$(PART_ID))
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synth: .prereqs
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$(call BUILD_VIVADO_DESIGN,$(TOOLS_DIR)/scripts/viv_synth.tcl,$(TOP_MODULE),$(ARCH),$(PART_ID))
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rtl: .prereqs
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$(call CHECK_VIVADO_DESIGN,$(TOOLS_DIR)/scripts/viv_check_syntax.tcl,$(TOP_MODULE),$(ARCH),$(PART_ID))
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viv_ip: show-var .prereqs $$(DESIGN_SRCS) ip
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@echo "IP build for $(NAME) DONE . . ."
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secure_core: .prereqs
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$(call BUILD_VIVADO_DESIGN,$(TOOLS_DIR)/scripts/viv_secure_synth.tcl,$(TOP_MODULE),$(ARCH),$(PART_ID))
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.PHONY: bin synth rtl viv_ip secure_synth_netlist
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