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Ryan Volz 1451ae066b fpga/usrp3: Fix DC truncation bias by adding rounding to DDC chain. 
A digital DC bias caused by various truncations in the DDC chain was
previously noticable with small signal levels, especially with high
decimation rates. This patch eliminates the bias by replacing the
truncation with rounding or simply keeping more bits for longer where it
makes sense.

This is essentially a forward port of a similar prior fix to the usrp2
DDC chain: https://github.com/EttusResearch/fpga/pull/4.

Signed-off-by: Ryan Volz <ryan.volz@gmail.com>


Original-commit: a57c162a0d11ab82a83c911a94272ceb6f7ff70a
2024-06-11 10:20:08 +02:00
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sim/sim_ddc_chain
Merge FPGA repository back into UHD repository
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acc.v
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add2_and_clip_reg.v
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add2_and_clip.v
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add2_and_round_reg.v
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add2_and_round.v
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add2_reg.v
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add2.v
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add_then_mac.v
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cic_dec_shifter.v
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cic_decim.v
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cic_int_shifter.v
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cic_interp.v
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cic_strober.v
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clip_reg.v
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clip.v
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cordic_stage.v
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cordic_z24.v
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ddc_chain.v
fpga/usrp3: Fix DC truncation bias by adding rounding to DDC chain.
2024-06-11 10:20:08 +02:00
duc_chain.v
Merge FPGA repository back into UHD repository
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hb47_int_tb.v
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hb47_int.v
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hb_dec.v
fpga/usrp3: Fix DC truncation bias by adding rounding to DDC chain.
2024-06-11 10:20:08 +02:00
hb_interp.v
Merge FPGA repository back into UHD repository
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Makefile.srcs
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mult_add_clip.v
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round_reg.v
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round_sd.v
fpga: lib: Update round_sd to eliminate X from simulation
2021-04-09 17:26:59 -05:00
round.v
Merge FPGA repository back into UHD repository
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rx_dcoffset.v
fpga: dsp: Fix formatting of rx_dcoffset and add docs
2021-03-09 08:33:32 -06:00
rx_frontend_tb.v
Merge FPGA repository back into UHD repository
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rx_frontend.v
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sign_extend.v
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small_hb_dec.v
fpga/usrp3: Fix DC truncation bias by adding rounding to DDC chain.
2024-06-11 10:20:08 +02:00
small_hb_int.v
Merge FPGA repository back into UHD repository
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srl.v
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tx_frontend.v
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variable_delay_line.v
fpga: rfnoc: Add Vector IIR RFNoC block
2020-05-19 14:22:55 -05:00