Javier Valenzuela
a6fc53b4e6
The main changes included are: - Variant-dependent pin-out instantiation. - Update clocking scheme in top level file to include XO3 PLL - Add ability to shift outgoing data for the GPIO communication interface with the X410 FPGA. - Include project files required to build the XO3 variant of the ZBX CPLD. - Add build flow for Lattice Diamond designs. - Add ability to build XO3 variant of ZBX CPLD. Original-commit: 2c7813acb21383f302353a1b6cf57f0946fa0b6b
34 lines
1.2 KiB
Makefile
34 lines
1.2 KiB
Makefile
#
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# Copyright 2022 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-2.0-or-later
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#
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include $(BASE_DIR)/../tools/make/diamond_preamble.mak
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SIMULATION = 0
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# -------------------------------------------------------------------
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# Usage: BUILD_DIAMOND_DESIGN
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# Args: $1 = PROJECT_NAME
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# $2 = PART_ID (LCMXO3LF-9400C, etc)
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# $3 = PROJECT_DIR (Absolute path to the top level project dir)
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# $4 = BUILD_DIR (Absolute path to the top level build dir)
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# $5 = IMPLEMENTATION_NAME (name of design implementation in project)
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# Prereqs:
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# - TOOLS_DIR must be defined globally
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# - DESIGN_SRCS must be defined and should contain all source files
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BUILD_DIAMOND_DESIGN = \
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@ \
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echo "========================================================"; \
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echo "BUILDER: Building $(1) for $(2)"; \
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echo "========================================================"; \
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echo "BUILDER: Staging Diamond sources in build directory..."; \
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cp -rf $(3)/lattice/* $(4)/;\
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cd $(4); \
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echo "BUILDER: Implementating design..."; \
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pnmainc build.tcl > $(1)_log.txt ; \
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echo "BUILDER: Generating bitfile..."; \
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ddtcmd -oft -svfsingle -if $(5)/$(1)_$(5).jed \
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-dev $(2) -op "FLASH Erase,Program,Verify" -revd \
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-of $(5)/$(1)_$(5).svf;
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