adf6f576c6
FPGA: - Split up MB registers that control daughterboard specific settings so that daughterboards 0 and 1 could have different setings, in preparation for future devices that require different settings. This requires a compat number bump to 8.0. - Add registers for additional RFDC information, including the block/tile mapping of the individual channels, and information about resampling capabilities - Identify sections of code that would be specific to X410/ZBX and move them to their own headers, so it's trivial to add device-specific sections of code instead for other devices in the future. - This includes constraints for clocks and I/O pins. - Remove ability to do timed ctrlport transactions to the MB CPLD, this was unused and possibly broken. - Move daughterboard-specific code into its own code location (dboards/zbx) - Move X410-specific register documentation to its own location (doc/X410) - Refactor Makefiles to split out X410/ZBX specific components and allow switching between device types - Add 512-bit AXI interconnects - Make number of timekeepers configurable (X410 keeps the single timekeeper) MPM: - Required compat is bumped to 8.0 - Now supports new registers for detecting DSP capabilities and multi-rate settings for the daughterboards - Adds MMCM controls (currently unused) Co-authored-by: Wade Fife <wade.fife@ni.com> Co-authored-by: Ryan Marlow <ryan@lmarlow.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Original-commit: c1d268917ea65dd9c5a42366014cb96d3c025223
42 lines
1.6 KiB
Systemverilog
42 lines
1.6 KiB
Systemverilog
//
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// Copyright 2023 Ettus Research, A National Instruments Company
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: pl_cpld_regmap_utils.vh
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// Description:
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// The constants in this file are autogenerated by XmlParse.
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//===============================================================================
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// A numerically ordered list of registers and their HDL source files
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//===============================================================================
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// BASE : 0x0 (cpld_interface.v)
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// MB_CPLD : 0x8000 (cpld_interface.v)
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// DB0_CPLD : 0x10000 (cpld_interface.v)
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// DB1_CPLD : 0x18000 (cpld_interface.v)
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//===============================================================================
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// RegTypes
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//===============================================================================
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//===============================================================================
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// Register Group PL_CPLD_WINDOWS
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//===============================================================================
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// BASE Window (from cpld_interface.v)
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localparam BASE = 'h0; // Window Offset
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localparam BASE_SIZE = 'h40; // size in bytes
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// MB_CPLD Window (from cpld_interface.v)
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localparam MB_CPLD = 'h8000; // Window Offset
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localparam MB_CPLD_SIZE = 'h8000; // size in bytes
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// DB0_CPLD Window (from cpld_interface.v)
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localparam DB0_CPLD = 'h10000; // Window Offset
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localparam DB0_CPLD_SIZE = 'h8000; // size in bytes
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// DB1_CPLD Window (from cpld_interface.v)
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localparam DB1_CPLD = 'h18000; // Window Offset
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localparam DB1_CPLD_SIZE = 'h8000; // size in bytes
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