54 lines
1.4 KiB
Systemverilog
54 lines
1.4 KiB
Systemverilog
//
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// Copyright 2020 Ettus Research, A National Instruments Company
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: ChdrIfaceBfm_all_tb
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//
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// Description:
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//
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// This is the top-level testbench that instantiates multiple instances of
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// the ChdrIfaceBfm_tb testbench to test different parameters.
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//
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module ChdrIfaceBfm_all_tb();
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`include "test_exec.svh"
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//---------------------------------------------------------------------------
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// Test Definitions
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//---------------------------------------------------------------------------
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typedef struct {
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int CHDR_W;
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int ITEM_W;
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} test_config_t;
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localparam NUM_TESTS = 8;
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localparam test_config_t tests[NUM_TESTS] = '{
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'{ CHDR_W: 64, ITEM_W: 8 },
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'{ CHDR_W: 64, ITEM_W: 16 },
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'{ CHDR_W: 64, ITEM_W: 32 },
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'{ CHDR_W: 64, ITEM_W: 64 },
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'{ CHDR_W: 128, ITEM_W: 8 },
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'{ CHDR_W: 128, ITEM_W: 16 },
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'{ CHDR_W: 128, ITEM_W: 32 },
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'{ CHDR_W: 128, ITEM_W: 64 }
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};
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//---------------------------------------------------------------------------
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// DUT Instances
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//---------------------------------------------------------------------------
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genvar i;
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for (i = 0; i < NUM_TESTS; i++) begin : gen_test_config
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ChdrIfaceBfm_tb #(
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.CHDR_W (tests[i].CHDR_W),
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.ITEM_W (tests[i].ITEM_W)
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) ChdrIfaceBfm_tb_i ();
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end : gen_test_config
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endmodule : ChdrIfaceBfm_all_tb
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