125 lines
4.4 KiB
Verilog
125 lines
4.4 KiB
Verilog
//
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// Copyright 2019 Ettus Research, A National Instruments brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: liberio_chdr64_adapter
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// Description: The transport adapter for a liberio transport with CHDR_W of
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// 64. A tuser field is used to identify the DMA engine for return routes.
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// The stream for a given SrcEPID with ID s_dma_tuser will return packets to
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// that EPID with same ID on m_dma_tuser (after an Advertise management
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// operation).
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//
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// Parameters:
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// - PROTOVER: RFNoC protocol version {8'd<major>, 8'd<minor>}
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// - RT_TBL_SIZE: Log2 of the depth of the return-address routing table
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// - NODE_INST: The node type to return for a node-info discovery
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// - DMA_ID_WIDTH: The width of the tuser signal that identifies the DMA engine)
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//
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// Signals:
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// - device_id : The ID of the device that has instantiated this module
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// - s_dma_*: The input DMA stream from the CPU (plus tuser for source DMA engine ID)
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// - m_dma_*: The output DMA stream to the CPU (plus tuser for dest DMA engine ID)
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// - s_chdr_*: The input CHDR stream from the rfnoc infrastructure
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// - m_chdr_*: The output CHDR stream to the rfnoc infrastructure
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//
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module liberio_chdr64_adapter #(
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parameter [15:0] PROTOVER = {8'd1, 8'd0},
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parameter RT_TBL_SIZE = 6,
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parameter NODE_INST = 0,
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parameter DMA_ID_WIDTH = 8
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)(
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// Clocking and reset interface
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input wire clk,
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input wire rst,
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// Device info
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input wire [15:0] device_id,
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// AXI-Stream interface to/from DMA engines
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input wire [63:0] s_dma_tdata,
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input wire [DMA_ID_WIDTH-1:0] s_dma_tuser,
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input wire s_dma_tlast,
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input wire s_dma_tvalid,
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output wire s_dma_tready,
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output wire [63:0] m_dma_tdata,
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output wire [DMA_ID_WIDTH-1:0] m_dma_tuser,
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output wire m_dma_tlast,
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output wire m_dma_tvalid,
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input wire m_dma_tready,
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// AXI-Stream interface to/from CHDR infrastructure
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input wire [63:0] s_chdr_tdata,
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input wire s_chdr_tlast,
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input wire s_chdr_tvalid,
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output wire s_chdr_tready,
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output wire [63:0] m_chdr_tdata,
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output wire m_chdr_tlast,
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output wire m_chdr_tvalid,
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input wire m_chdr_tready
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);
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`include "../core/rfnoc_chdr_utils.vh"
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`include "../core/rfnoc_chdr_internal_utils.vh"
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`include "rfnoc_xport_types.vh"
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//---------------------------------------
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// CHDR Transport Adapter
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//---------------------------------------
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wire [DMA_ID_WIDTH-1:0] m_axis_xport_tuser;
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chdr_xport_adapter_generic #(
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.PROTOVER (PROTOVER),
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.CHDR_W (64),
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.USER_W (DMA_ID_WIDTH),
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.TBL_SIZE (RT_TBL_SIZE),
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.NODE_SUBTYPE (NODE_SUBTYPE_XPORT_LIBERIO_CHDR64),
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.NODE_INST (NODE_INST),
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.ALLOW_DISC (0)
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) xport_adapter_gen_i (
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.clk (clk),
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.rst (rst),
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.device_id (device_id),
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.s_axis_xport_tdata (s_dma_tdata),
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.s_axis_xport_tuser (s_dma_tuser),
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.s_axis_xport_tlast (s_dma_tlast),
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.s_axis_xport_tvalid (s_dma_tvalid),
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.s_axis_xport_tready (s_dma_tready),
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.m_axis_xport_tdata (m_dma_tdata),
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.m_axis_xport_tuser (m_axis_xport_tuser),
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.m_axis_xport_tlast (m_dma_tlast),
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.m_axis_xport_tvalid (m_dma_tvalid),
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.m_axis_xport_tready (m_dma_tready),
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.s_axis_rfnoc_tdata (s_chdr_tdata),
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.s_axis_rfnoc_tlast (s_chdr_tlast),
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.s_axis_rfnoc_tvalid (s_chdr_tvalid),
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.s_axis_rfnoc_tready (s_chdr_tready),
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.m_axis_rfnoc_tdata (m_chdr_tdata),
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.m_axis_rfnoc_tlast (m_chdr_tlast),
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.m_axis_rfnoc_tvalid (m_chdr_tvalid),
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.m_axis_rfnoc_tready (m_chdr_tready),
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.ctrlport_req_wr (/* unused */),
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.ctrlport_req_rd (/* unused */),
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.ctrlport_req_addr (/* unused */),
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.ctrlport_req_data (/* unused */),
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.ctrlport_resp_ack (/* unused */ 1'b0),
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.ctrlport_resp_data (/* unused */ 32'd0)
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);
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// Ensure tdest does not change for entire packet
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reg m_hdr = 1'b1;
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always @(posedge clk) begin
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if (rst)
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m_hdr <= 1'b1;
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else if (m_dma_tvalid && m_dma_tready)
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m_hdr <= m_dma_tlast;
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end
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reg [DMA_ID_WIDTH-1:0] cached_dest = {DMA_ID_WIDTH{1'b0}};
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always @(posedge clk) begin
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if (m_hdr)
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cached_dest <= m_axis_xport_tuser;
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end
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assign m_dma_tuser = m_hdr ? m_axis_xport_tuser : cached_dest;
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endmodule // liberio_chdr64_adapter
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