98 lines
3.2 KiB
Verilog
98 lines
3.2 KiB
Verilog
//
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// Copyright 2016 Ettus Research
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// Copyright 2018 Ettus Research, a National Instruments Company
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Settings register with AXI stream output.
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//
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// Parameters / common use cases:
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// USE_ADDR_LAST & ADDR_LAST User wants additional address that when written to asserts tlast.
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// Useful for the last word in a packet.
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// USE_FIFO & FIFO_SIZE Downstream block can throttle and a FIFO is needed to handle that case.
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// STROBE_LAST User always wants to assert tlast on writes. More efficient than USE_ADDR_LAST
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// since only one address is used instead of two.
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// REPEATS Keep tvalid asserted after initial write.
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// STROBE_LAST & REPEATS tlast is asserted on the initial write then deasserted for repeating output.
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// MSB_ALIGN Left justify data versus right justify.
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module axi_setting_reg #(
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parameter ADDR = 0,
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parameter USE_ADDR_LAST = 0,
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parameter ADDR_LAST = ADDR+1,
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parameter AWIDTH = 8,
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parameter WIDTH = 32,
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parameter USE_FIFO = 0,
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parameter FIFO_SIZE = 5,
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parameter DATA_AT_RESET = 0,
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parameter VALID_AT_RESET = 0,
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parameter LAST_AT_RESET = 0,
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parameter STROBE_LAST = 0,
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parameter REPEATS = 0,
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parameter MSB_ALIGN = 0
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)
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(
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input clk, input reset, output reg error_stb,
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input set_stb, input [AWIDTH-1:0] set_addr, input [31:0] set_data,
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output [WIDTH-1:0] o_tdata, output o_tlast, output o_tvalid, input o_tready
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);
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reg init;
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reg [WIDTH-1:0] o_tdata_int;
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reg o_tlast_int, o_tvalid_int = VALID_AT_RESET;
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wire o_tready_int;
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always @(posedge clk) begin
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if (reset) begin
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o_tdata_int <= DATA_AT_RESET;
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o_tvalid_int <= VALID_AT_RESET;
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o_tlast_int <= LAST_AT_RESET;
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init <= 1'b0;
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error_stb <= 1'b0;
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end else begin
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error_stb <= 1'b0;
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if (o_tvalid_int & o_tready_int) begin
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// Deassert tvalid / tlast only if not repeating the output
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if (REPEATS == 0) begin
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o_tvalid_int <= 1'b0;
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end
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if ((REPEATS == 0) | (STROBE_LAST == 1)) begin
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o_tlast_int <= 1'b0;
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end
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end
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if (set_stb & ((ADDR[AWIDTH-1:0] == set_addr) | (USE_ADDR_LAST & (ADDR_LAST[AWIDTH-1:0] == set_addr)))) begin
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init <= 1'b1;
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o_tdata_int <= (MSB_ALIGN == 0) ? set_data[WIDTH-1:0] : set_data[31:32-WIDTH];
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o_tvalid_int <= 1'b1;
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if (set_stb & (STROBE_LAST | (USE_ADDR_LAST & (ADDR_LAST[AWIDTH-1:0] == set_addr)))) begin
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o_tlast_int <= 1'b1;
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end else begin
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o_tlast_int <= 1'b0;
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end
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if (~o_tready_int) begin
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error_stb <= 1'b1;
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end
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end
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end
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end
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generate
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if (USE_FIFO) begin
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axi_fifo #(
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.WIDTH(WIDTH+1), .SIZE(FIFO_SIZE))
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axi_fifo (
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.clk(clk), .reset(reset), .clear(1'b0),
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.i_tdata({o_tlast_int,o_tdata_int}), .i_tvalid(o_tvalid_int), .i_tready(o_tready_int),
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.o_tdata({o_tlast,o_tdata}), .o_tvalid(o_tvalid), .o_tready(o_tready),
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.space(), .occupied());
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end else begin
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assign o_tdata = o_tdata_int;
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assign o_tlast = o_tlast_int;
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assign o_tvalid = o_tvalid_int;
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assign o_tready_int = o_tready;
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end
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endgenerate
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endmodule
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