5cadf901c7
Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Wade Fife <wade.fife@ni.com> Co-authored-by: Ryan Marlow <ryan@lmarlow.com> Original-commit: 596760a12e4834e47589c12f8a4fd083aa2f7c25
31 lines
1.2 KiB
Systemverilog
31 lines
1.2 KiB
Systemverilog
//
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// Copyright 2022 Ettus Research, A National Instruments Company
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: clock_en_regmap_utils.vh
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// Description:
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// The constants in this file are autogenerated by XmlParse.
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//===============================================================================
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// A numerically ordered list of registers and their HDL source files
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//===============================================================================
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// CLK_EN_CONTROL : 0x0 (clock_en_control.v)
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//===============================================================================
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// RegTypes
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//===============================================================================
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//===============================================================================
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// Register Group CLOCK_EN_REGISTERS
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//===============================================================================
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// CLK_EN_CONTROL Register (from clock_en_control.v)
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localparam CLK_EN_CONTROL = 'h0; // Register Offset
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localparam CLK_EN_CONTROL_SIZE = 32; // register width in bits
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localparam CLK_EN_CONTROL_MASK = 32'h1;
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localparam CLK_EN_SIZE = 1; //CLK_EN_CONTROL:CLK_EN
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localparam CLK_EN_MSB = 0; //CLK_EN_CONTROL:CLK_EN
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localparam CLK_EN = 0; //CLK_EN_CONTROL:CLK_EN
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