Wade Fife d16d1e121c fpga: Update RFNOC_EDGE_TBL_FILE for Cygwin ...

Original-commit: 7f5f771796de590c4ed4bba7b09cda3a906535c6

2020-06-12 15:50:16 -05:00

..

dts

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

ip

fpga: e31x: Replace symbolic link for Cygwin

2020-05-12 13:47:20 -05:00

sim

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

axi_pmu.v

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

build_e31x.tcl

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

e31x_core.v

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

e31x_idle_pins.xdc

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

e31x_idle.v

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

e31x_pins.xdc

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

e31x_rfnoc_image_core.v

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

e31x_rfnoc_image_core.yml

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

e31x_timing.xdc

fpga: e31x: Update constraints to avoid timing issues

2020-04-08 17:24:15 -05:00

e31x.v

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

e310_io.v

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

e310_static_router.hex

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

Makefile

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

Makefile.e31x.inc

fpga: Update RFNOC_EDGE_TBL_FILE for Cygwin

2020-06-12 15:50:16 -05:00

ppsloop.v

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

setupenv.sh

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

spi_slave.v

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00