Wade Fife
1756797ec2
The NODE_INST parameter was set to 0. This adds it as a parameter so that each transport adapter can have a unique node instance number. Original-commit: c6bfd2e7f8313d727c2e557958f1b1ac2f674d98
435 lines
14 KiB
Verilog
435 lines
14 KiB
Verilog
///////////////////////////////////////////////////////////////////
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//
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// Copyright 2019 Ettus Research, a National Instruments brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: eth_internal
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// Description:
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// Reduces clutter at top level.
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// - FPGA-internal Ethernet port
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// - ARP responder instead of other CPU connection
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//
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//////////////////////////////////////////////////////////////////////
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`default_nettype none
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module eth_internal #(
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parameter DWIDTH = 32,
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parameter AWIDTH = 14,
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parameter [7:0] PORTNUM = 0,
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parameter [15:0] RFNOC_PROTOVER = {8'd1, 8'd0},
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parameter NODE_INST = 0
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)(
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// Resets
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input wire bus_rst,
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// Clocks
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input wire bus_clk,
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//Axi-lite
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input wire s_axi_aclk,
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input wire s_axi_aresetn,
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input wire [AWIDTH-1:0] s_axi_awaddr,
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input wire s_axi_awvalid,
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output wire s_axi_awready,
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input wire [DWIDTH-1:0] s_axi_wdata,
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input wire [DWIDTH/8-1:0] s_axi_wstrb,
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input wire s_axi_wvalid,
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output wire s_axi_wready,
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output wire [1:0] s_axi_bresp,
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output wire s_axi_bvalid,
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input wire s_axi_bready,
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input wire [AWIDTH-1:0] s_axi_araddr,
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input wire s_axi_arvalid,
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output wire s_axi_arready,
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output wire [DWIDTH-1:0] s_axi_rdata,
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output wire [1:0] s_axi_rresp,
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output wire s_axi_rvalid,
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input wire s_axi_rready,
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// Host-Ethernet DMA interface
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output wire [63:0] e2h_tdata,
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output wire [7:0] e2h_tkeep,
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output wire e2h_tlast,
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output wire e2h_tvalid,
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input wire e2h_tready,
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input wire [63:0] h2e_tdata,
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input wire [7:0] h2e_tkeep,
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input wire h2e_tlast,
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input wire h2e_tvalid,
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output wire h2e_tready,
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// RFNoC interface
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output wire [63:0] e2v_tdata,
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output wire e2v_tlast,
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output wire e2v_tvalid,
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input wire e2v_tready,
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input wire [63:0] v2e_tdata,
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input wire v2e_tlast,
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input wire v2e_tvalid,
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output wire v2e_tready,
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// MISC
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output wire [31:0] port_info,
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input wire [15:0] device_id,
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output wire link_up,
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output reg activity
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);
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localparam REG_BASE_ETH_IO = 14'h0;
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localparam REG_BASE_ETH_SWITCH = 14'h1000;
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// AXI4-Lite to RegPort (PS to PL Register Access)
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wire reg_wr_req;
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wire [AWIDTH-1:0] reg_wr_addr;
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wire [DWIDTH-1:0] reg_wr_data;
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wire reg_rd_req;
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wire [AWIDTH-1:0] reg_rd_addr;
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wire reg_rd_resp, reg_rd_resp_eth_if;
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reg reg_rd_resp_io = 1'b0;
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wire [DWIDTH-1:0] reg_rd_data, reg_rd_data_eth_if;
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reg [DWIDTH-1:0] reg_rd_data_io = 'd0;
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axil_regport_master #(
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.DWIDTH (DWIDTH), // Width of the AXI4-Lite data bus (must be 32 or 64)
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.AWIDTH (AWIDTH), // Width of the address bus
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.WRBASE (0), // Write address base
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.RDBASE (0), // Read address base
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.TIMEOUT (10) // log2(timeout). Read will timeout after (2^TIMEOUT - 1) cycles
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) eth_dma_reg_mst_i (
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// Clock and reset
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.s_axi_aclk (s_axi_aclk),
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.s_axi_aresetn (s_axi_aresetn),
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// AXI4-Lite: Write address port (domain: s_axi_aclk)
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.s_axi_awaddr (s_axi_awaddr),
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.s_axi_awvalid (s_axi_awvalid),
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.s_axi_awready (s_axi_awready),
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// AXI4-Lite: Write data port (domain: s_axi_aclk)
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.s_axi_wdata (s_axi_wdata),
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.s_axi_wstrb (s_axi_wstrb),
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.s_axi_wvalid (s_axi_wvalid),
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.s_axi_wready (s_axi_wready),
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// AXI4-Lite: Write response port (domain: s_axi_aclk)
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.s_axi_bresp (s_axi_bresp),
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.s_axi_bvalid (s_axi_bvalid),
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.s_axi_bready (s_axi_bready),
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// AXI4-Lite: Read address port (domain: s_axi_aclk)
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.s_axi_araddr (s_axi_araddr),
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.s_axi_arvalid (s_axi_arvalid),
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.s_axi_arready (s_axi_arready),
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// AXI4-Lite: Read data port (domain: s_axi_aclk)
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.s_axi_rdata (s_axi_rdata),
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.s_axi_rresp (s_axi_rresp),
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.s_axi_rvalid (s_axi_rvalid),
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.s_axi_rready (s_axi_rready),
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// Register port: Write port (domain: reg_clk)
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.reg_clk (bus_clk),
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.reg_wr_req (reg_wr_req),
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.reg_wr_addr (reg_wr_addr),
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.reg_wr_data (reg_wr_data),
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// Register port: Read port (domain: reg_clk)
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.reg_rd_req (reg_rd_req),
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.reg_rd_addr (reg_rd_addr),
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.reg_rd_resp (reg_rd_resp),
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.reg_rd_data (reg_rd_data)
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);
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// Regport Mux for response
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regport_resp_mux #(
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.WIDTH (DWIDTH),
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.NUM_SLAVES (2)
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) reg_resp_mux_i (
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.clk(bus_clk), .reset(bus_rst),
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.sla_rd_resp({reg_rd_resp_eth_if, reg_rd_resp_io}),
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.sla_rd_data({reg_rd_data_eth_if, reg_rd_data_io}),
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.mst_rd_resp(reg_rd_resp), .mst_rd_data(reg_rd_data)
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);
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// ARP responder
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wire [63:0] e2c_tdata;
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wire [7:0] e2c_tkeep;
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wire e2c_tlast;
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wire e2c_tvalid;
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wire e2c_tready;
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wire [63:0] c2e_tdata;
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wire [7:0] c2e_tkeep;
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wire c2e_tlast;
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wire c2e_tvalid;
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wire c2e_tready;
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wire [3:0] e2c_tuser;
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wire [3:0] c2e_tuser;
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// ARM Host-to-Ethernet
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wire [3:0] e2h_tuser;
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wire [3:0] h2e_tuser;
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// Host Ethernet-to-CHDR
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wire [63:0] h2e_chdr_tdata;
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wire [3:0] h2e_chdr_tuser;
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wire h2e_chdr_tlast;
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wire h2e_chdr_tvalid;
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wire h2e_chdr_tready;
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wire [63:0] e2h_chdr_tdata;
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wire [3:0] e2h_chdr_tuser;
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wire e2h_chdr_tlast;
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wire e2h_chdr_tvalid;
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wire e2h_chdr_tready;
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// In AXI Stream, tkeep is the byte qualifier that indicates
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// whether the content of the associated byte
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// of TDATA is processed as part of the data stream.
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// tuser as used in eth_interface is the number of valid bytes
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// Converting tuser to tkeep for ingress packets
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assign e2c_tkeep = ~e2c_tlast ? 8'b1111_1111
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: (e2c_tuser == 4'd0) ? 8'b1111_1111
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: (e2c_tuser == 4'd1) ? 8'b0000_0001
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: (e2c_tuser == 4'd2) ? 8'b0000_0011
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: (e2c_tuser == 4'd3) ? 8'b0000_0111
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: (e2c_tuser == 4'd4) ? 8'b0000_1111
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: (e2c_tuser == 4'd5) ? 8'b0001_1111
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: (e2c_tuser == 4'd6) ? 8'b0011_1111
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: 8'b0111_1111;
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// Converting tkeep to tuser for egress packets
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assign c2e_tuser = ~c2e_tlast ? 4'd0
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: (c2e_tkeep == 8'b1111_1111) ? 4'd0
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: (c2e_tkeep == 8'b0111_1111) ? 4'd7
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: (c2e_tkeep == 8'b0011_1111) ? 4'd6
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: (c2e_tkeep == 8'b0001_1111) ? 4'd5
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: (c2e_tkeep == 8'b0000_1111) ? 4'd4
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: (c2e_tkeep == 8'b0000_0111) ? 4'd3
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: (c2e_tkeep == 8'b0000_0011) ? 4'd2
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: (c2e_tkeep == 8'b0000_0001) ? 4'd1
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: 4'd0;
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// Converting tuser to tkeep for ingress packets
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assign e2h_tkeep = ~e2h_tlast ? 8'b1111_1111
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: (e2h_tuser == 4'd0) ? 8'b1111_1111
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: (e2h_tuser == 4'd1) ? 8'b0000_0001
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: (e2h_tuser == 4'd2) ? 8'b0000_0011
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: (e2h_tuser == 4'd3) ? 8'b0000_0111
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: (e2h_tuser == 4'd4) ? 8'b0000_1111
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: (e2h_tuser == 4'd5) ? 8'b0001_1111
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: (e2h_tuser == 4'd6) ? 8'b0011_1111
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: 8'b0111_1111;
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// Converting tkeep to tuser for egress packets
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assign h2e_tuser = ~h2e_tlast ? 4'd0
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: (h2e_tkeep == 8'b1111_1111) ? 4'd0
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: (h2e_tkeep == 8'b0111_1111) ? 4'd7
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: (h2e_tkeep == 8'b0011_1111) ? 4'd6
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: (h2e_tkeep == 8'b0001_1111) ? 4'd5
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: (h2e_tkeep == 8'b0000_1111) ? 4'd4
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: (h2e_tkeep == 8'b0000_0111) ? 4'd3
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: (h2e_tkeep == 8'b0000_0011) ? 4'd2
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: (h2e_tkeep == 8'b0000_0001) ? 4'd1
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: 4'd0;
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// FPGA-side addresses for the ARP responder
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wire [47:0] my_mac;
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wire [31:0] my_ip;
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wire [15:0] my_udp_port;
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arm_deframer arm_deframer_i (
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.clk(bus_clk),
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.reset(bus_rst),
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.clear(1'b0),
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.s_axis_tdata(h2e_tdata),
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.s_axis_tuser(h2e_tuser),
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.s_axis_tlast(h2e_tlast),
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.s_axis_tvalid(h2e_tvalid),
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.s_axis_tready(h2e_tready),
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.m_axis_tdata(h2e_chdr_tdata),
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.m_axis_tuser(h2e_chdr_tuser),
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.m_axis_tlast(h2e_chdr_tlast),
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.m_axis_tvalid(h2e_chdr_tvalid),
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.m_axis_tready(h2e_chdr_tready)
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);
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axi64_to_xge64 arm_framer (
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.clk(bus_clk),
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.reset(bus_rst),
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.clear(1'b0),
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.s_axis_tdata(e2h_chdr_tdata),
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.s_axis_tuser(e2h_chdr_tuser),
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.s_axis_tlast(e2h_chdr_tlast),
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.s_axis_tvalid(e2h_chdr_tvalid),
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.s_axis_tready(e2h_chdr_tready),
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.m_axis_tdata(e2h_tdata),
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.m_axis_tuser(e2h_tuser),
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.m_axis_tlast(e2h_tlast),
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.m_axis_tvalid(e2h_tvalid),
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.m_axis_tready(e2h_tready)
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);
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eth_interface #(
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.PROTOVER(RFNOC_PROTOVER),
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.MTU(10),
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.NODE_INST(NODE_INST),
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.REG_AWIDTH (AWIDTH),
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.BASE(REG_BASE_ETH_SWITCH)
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) eth_interface (
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.clk (bus_clk),
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.reset (bus_rst),
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.device_id (device_id),
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.reg_wr_req (reg_wr_req),
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.reg_wr_addr (reg_wr_addr),
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.reg_wr_data (reg_wr_data),
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.reg_rd_req (reg_rd_req),
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.reg_rd_addr (reg_rd_addr),
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.reg_rd_resp (reg_rd_resp_eth_if),
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.reg_rd_data (reg_rd_data_eth_if),
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.my_mac (my_mac),
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.my_ip (my_ip),
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.my_udp_port (my_udp_port),
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.eth_tx_tdata (e2h_chdr_tdata),
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.eth_tx_tuser (e2h_chdr_tuser),
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.eth_tx_tlast (e2h_chdr_tlast),
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.eth_tx_tvalid (e2h_chdr_tvalid),
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.eth_tx_tready (e2h_chdr_tready),
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.eth_rx_tdata (h2e_chdr_tdata),
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.eth_rx_tuser (h2e_chdr_tuser),
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.eth_rx_tlast (h2e_chdr_tlast),
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.eth_rx_tvalid (h2e_chdr_tvalid),
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.eth_rx_tready (h2e_chdr_tready),
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.e2v_tdata (e2v_tdata),
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.e2v_tlast (e2v_tlast),
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.e2v_tvalid (e2v_tvalid),
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.e2v_tready (e2v_tready),
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.v2e_tdata (v2e_tdata),
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.v2e_tlast (v2e_tlast),
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.v2e_tvalid (v2e_tvalid),
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.v2e_tready (v2e_tready),
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.e2c_tdata (e2c_tdata),
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.e2c_tuser (e2c_tuser),
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.e2c_tlast (e2c_tlast),
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.e2c_tvalid (e2c_tvalid),
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.e2c_tready (e2c_tready),
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.c2e_tdata (c2e_tdata),
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.c2e_tuser (c2e_tuser),
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.c2e_tlast (c2e_tlast),
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.c2e_tvalid (c2e_tvalid),
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.c2e_tready (c2e_tready)
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);
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arp_responder arp_responder_i (
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.aclk (bus_clk),
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.aresetn (~bus_rst),
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.mac_addr (my_mac),
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.ip_addr (my_ip),
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.s_axis_tdata (e2c_tdata),
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.s_axis_tvalid (e2c_tvalid),
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.s_axis_tready (e2c_tready),
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.s_axis_tkeep (e2c_tkeep),
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.s_axis_tlast (e2c_tlast),
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.s_axis_tuser (1'b0),
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.m_axis_tdata (c2e_tdata),
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.m_axis_tvalid (c2e_tvalid),
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.m_axis_tready (c2e_tready),
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.m_axis_tkeep (c2e_tkeep),
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.m_axis_tlast (c2e_tlast),
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.m_axis_tuser ()
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);
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//-----------------------------------------------------------------
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// "I/O" Registers
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//-----------------------------------------------------------------
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localparam [7:0] COMPAT_NUM = 8'd2;
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localparam [7:0] MGT_PROTOCOL = 8'd4; // 10 GbE Internal (8'd2 is 10 GbE External)
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// Common registers
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localparam REG_PORT_INFO = REG_BASE_ETH_IO + 'h0;
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localparam REG_MAC_CTRL_STATUS = REG_BASE_ETH_IO + 'h4;
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localparam REG_PHY_CTRL_STATUS = REG_BASE_ETH_IO + 'h8;
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localparam REG_MAC_LED_CTL = REG_BASE_ETH_IO + 'hC;
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// Protocol specific constants
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localparam [1:0] MAC_LED_CTL_RST_VAL = 2'h0;
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localparam [31:0] MAC_CTRL_RST_VAL = {31'h0, 1'b1}; // tx_enable on reset
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localparam [31:0] PHY_CTRL_RST_VAL = 32'h0;
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// Writable registers
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reg [31:0] mac_ctrl_reg = MAC_CTRL_RST_VAL;
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reg [31:0] phy_ctrl_reg = PHY_CTRL_RST_VAL;
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reg [1:0] mac_led_ctl = MAC_LED_CTL_RST_VAL;
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always @(posedge bus_clk) begin
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if (bus_rst) begin
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mac_ctrl_reg <= MAC_CTRL_RST_VAL;
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phy_ctrl_reg <= PHY_CTRL_RST_VAL;
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mac_led_ctl <= MAC_LED_CTL_RST_VAL;
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end else if (reg_wr_req) begin
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case(reg_wr_addr)
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REG_MAC_CTRL_STATUS:
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mac_ctrl_reg <= reg_wr_data;
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REG_PHY_CTRL_STATUS:
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phy_ctrl_reg <= reg_wr_data;
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REG_MAC_LED_CTL:
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mac_led_ctl <= reg_wr_data[1:0];
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endcase
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end
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end
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// Readable registers
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wire [31:0] mac_status, phy_status;
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assign port_info = {COMPAT_NUM, 6'h0, activity, link_up, MGT_PROTOCOL, PORTNUM};
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always @(posedge bus_clk) begin
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// No reset handling needed for readback
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if (reg_rd_req) begin
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reg_rd_resp_io <= 1'b1;
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case(reg_rd_addr)
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REG_PORT_INFO:
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reg_rd_data_io <= port_info;
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REG_MAC_CTRL_STATUS:
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reg_rd_data_io <= mac_status;
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REG_PHY_CTRL_STATUS:
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reg_rd_data_io <= phy_status;
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REG_MAC_LED_CTL:
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reg_rd_data_io <= {30'd0, mac_led_ctl};
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default:
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reg_rd_resp_io <= 1'b0;
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endcase
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end if (reg_rd_resp_io) begin
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reg_rd_resp_io <= 1'b0;
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end
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end
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assign mac_status = 'd0;
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assign phy_status[31:8] = 24'h0;
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assign link_up = 1'b1;
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wire identify_enable = mac_led_ctl[0];
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wire identify_value = mac_led_ctl[1];
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//-----------------------------------------------------------------
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// Activity detector
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//-----------------------------------------------------------------
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wire activity_int;
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pulse_stretch act_pulse_str_i (
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.clk(bus_clk),
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.rst(bus_rst | ~link_up),
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.pulse((h2e_tvalid & h2e_tready) | (e2h_tvalid & e2h_tready)),
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.pulse_stretched(activity_int)
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);
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always @ (posedge bus_clk) activity <= identify_enable ? identify_value : activity_int;
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endmodule
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`default_nettype wire
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