31 lines
1.1 KiB
Verilog
31 lines
1.1 KiB
Verilog
///////////////////////////////////////////////////////////////////////////////
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// Copyright (c) 2013 Xilinx, Inc.
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// All Rights Reserved
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///////////////////////////////////////////////////////////////////////////////
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor : Xilinx
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// \ \ \/ Version : 14.4
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// \ \ Application: Xilinx CORE Generator
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// / / Filename : chipscope_ila_32.veo
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// /___/ /\ Timestamp : Fri Mar 08 11:59:29 PST 2013
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// \ \ / \
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// \___\/\___\
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//
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// Design Name: ISE Instantiation template
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///////////////////////////////////////////////////////////////////////////////
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// The following must be inserted into your Verilog file for this
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// core to be instantiated. Change the instance name and port connections
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// (in parentheses) to your own signal names.
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//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
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chipscope_ila_32 YourInstanceName (
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.CONTROL(CONTROL), // INOUT BUS [35:0]
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.CLK(CLK), // IN
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.TRIG0(TRIG0) // IN BUS [31:0]
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);
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// INST_TAG_END ------ End INSTANTIATION Template ---------
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