110 lines
1.9 KiB
Verilog
110 lines
1.9 KiB
Verilog
`timescale 1ns/1ps
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module catcap_tb();
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wire GSR, GTS;
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glbl glbl( );
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reg clk = 0;
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reg ddrclk = 0;
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reg reset = 1;
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always #100 clk = ~clk;
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always @(negedge clk) ddrclk <= ~ddrclk;
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initial $dumpfile("catcap_tb.vcd");
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initial $dumpvars(0,catcap_tb);
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wire [11:0] i0 = {4'hA,count};
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wire [11:0] q0 = {4'hB,count};
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wire [11:0] i1 = {4'hC,count};
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wire [11:0] q1 = {4'hD,count};
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reg mimo;
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reg [11:0] pins;
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reg frame;
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reg [7:0] count;
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initial
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begin
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#1000 reset = 0;
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MIMO_BURST(4);
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MIMO_BURST(5);
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BURST(4);
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BURST(5);
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#2000;
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$finish;
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end
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task BURST;
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input [7:0] len;
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begin
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frame <= 0;
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@(posedge clk);
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@(posedge clk);
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mimo <= 0;
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@(posedge clk);
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@(posedge clk);
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@(posedge clk);
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@(posedge ddrclk);
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count <= 0;
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repeat(len)
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begin
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@(posedge clk);
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pins <= i0;
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frame <= 1;
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@(posedge clk);
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pins <= q0;
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frame <= 0;
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count <= count + 1;
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end
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end
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endtask // BURST
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task MIMO_BURST;
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input [7:0] len;
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begin
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frame <= 0;
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@(posedge clk);
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@(posedge clk);
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mimo <= 1;
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@(posedge clk);
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@(posedge clk);
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@(posedge clk);
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@(posedge ddrclk);
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count <= 0;
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repeat(len)
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begin
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@(posedge clk);
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pins <= i0;
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frame <= 1;
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@(posedge clk);
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pins <= q0;
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@(posedge clk);
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pins <= i1;
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frame <= 0;
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@(posedge clk);
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pins <= q1;
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count <= count + 1;
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end
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@(posedge clk);
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@(posedge clk);
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end
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endtask // MIMO_BURST
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wire rx_clk, rx_strobe;
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wire [11:0] i0o,i1o,q0o,q1o;
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catcap_ddr_cmos catcap
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(.data_clk(ddrclk),
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.reset(reset),
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.mimo(mimo),
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.rx_frame(frame),
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.rx_d(pins),
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.rx_clk(rx_clk),
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.rx_strobe(rx_strobe),
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.i0(i0o),.q0(q0o),
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.i1(i1o),.q1(q1o));
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endmodule // hb_chain_tb
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