24 lines
675 B
Verilog
24 lines
675 B
Verilog
module S6CLK2PIN
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(
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input I,
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output O
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);
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ODDR2 #(
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.DDR_ALIGNMENT("NONE"), // to "NONE", "C0" or "C1"
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.INIT(1'b0), // output to 1'b0 or 1'b1
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.SRTYPE("ASYNC")) // set/reset "SYNC" or "ASYNC"
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ODDR2_S6CLK2PIN
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(
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.Q(O), // 1-bit DDR output data
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.C0(I), // 1-bit clock input
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.C1(~I), // 1-bit clock input
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.CE(1'b1), // 1-bit clock enable input
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.D0(1'b1), // 1-bit data input (associated with C0)
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.D1(1'b0), // 1-bit data input (associated with C1)
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.R(1'b0), // 1-bit reset input
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.S(1'b0) );// 1-bit set input
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endmodule //S6CLK2PIN
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