39 lines
1.1 KiB
Verilog
39 lines
1.1 KiB
Verilog
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module axi_fifo32_to_fifo64
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(input clk, input reset, input clear,
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input [31:0] i_tdata, input [1:0] i_tuser, input i_tlast, input i_tvalid, output i_tready,
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output [63:0] o_tdata, output [2:0] o_tuser, output o_tlast, output o_tvalid, input o_tready
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);
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reg [31:0] holding;
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reg state;
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always @(posedge clk)
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if(reset | clear)
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state <= 0;
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else
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if(i_tvalid & i_tready)
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case(state)
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0 : if(~i_tlast) state <= 1'b1;
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1 : state <= 1'b0;
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default : state <= 1'b0;
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endcase // case (state)
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always @(posedge clk)
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if(i_tvalid & i_tready)
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holding <= i_tdata;
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assign i_tready = (state == 0 && !i_tlast)? 1'b1 : o_tready;
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assign o_tvalid = (state == 0 && !i_tlast)? 1'b0 : i_tvalid;
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assign o_tdata = (state == 0) ? {i_tdata, 32'h0} : { holding, i_tdata };
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assign o_tlast = i_tlast;
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wire [2:0] occ_in = (i_tuser == 0) ? 3'd4 : {1'b0, i_tuser};
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wire [2:0] occ_out = (state == 0) ? occ_in : (occ_in + 3'd4);
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assign o_tuser = ~o_tlast ? 3'd0 : occ_out;
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endmodule // axi_fifo32_to_fifo64
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