miegl
286cde0a8d
Replace broad GPIF/radio false paths with 10 ns datapath-only maximum delays between the 100 MHz GPIF clock and the generated SISO/MIMO radio clocks. Preserve physical control of asynchronous CDC paths without overriding the more-specific XPM FIFO CDC constraints.
240 lines
15 KiB
Tcl
240 lines
15 KiB
Tcl
set_property -dict {PACKAGE_PIN G11 IOSTANDARD LVCMOS33} [get_ports PPS_IN_EXT]
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set_property -dict {PACKAGE_PIN B15 IOSTANDARD LVCMOS33} [get_ports PPS_IN_INT]
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set_property -dict {PACKAGE_PIN AA17 IOSTANDARD LVDS} [get_ports codec_main_clk_p]
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set_property -dict {PACKAGE_PIN AA18 IOSTANDARD LVDS} [get_ports codec_main_clk_n]
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set_property -dict {PACKAGE_PIN A8 IOSTANDARD LVCMOS33} [get_ports pll_ce]
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set_property -dict {PACKAGE_PIN C9 IOSTANDARD LVCMOS33} [get_ports pll_mosi]
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set_property -dict {PACKAGE_PIN A9 IOSTANDARD LVCMOS33} [get_ports pll_sclk]
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set_property -dict {PACKAGE_PIN D9 IOSTANDARD LVCMOS33} [get_ports ref_sel]
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set_property -dict {PACKAGE_PIN D8 IOSTANDARD LVCMOS33} [get_ports pll_lock]
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# set_property -dict {PACKAGE_PIN A14 IOSTANDARD LVCMOS33} [get_ports gps_rxd]
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# set_property -dict {PACKAGE_PIN B14 IOSTANDARD LVCMOS33} [get_ports gps_txd]
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# #### FX3 Lines ##############################################################
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# GPIF Data lines
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set_property -dict {PACKAGE_PIN U6 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[0]}]
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set_property -dict {PACKAGE_PIN AA3 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[1]}]
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set_property -dict {PACKAGE_PIN V6 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[2]}]
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set_property -dict {PACKAGE_PIN U5 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[3]}]
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set_property -dict {PACKAGE_PIN V3 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[4]}]
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set_property -dict {PACKAGE_PIN U1 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[5]}]
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set_property -dict {PACKAGE_PIN V4 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[6]}]
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set_property -dict {PACKAGE_PIN W4 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[7]}]
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set_property -dict {PACKAGE_PIN W6 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[8]}]
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set_property -dict {PACKAGE_PIN W1 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[9]}]
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set_property -dict {PACKAGE_PIN Y6 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[10]}]
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set_property -dict {PACKAGE_PIN AB2 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[11]}]
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set_property -dict {PACKAGE_PIN AA5 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[12]}]
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set_property -dict {PACKAGE_PIN Y3 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[13]}]
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set_property -dict {PACKAGE_PIN AC1 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[14]}]
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set_property -dict {PACKAGE_PIN AA2 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[15]}]
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set_property -dict {PACKAGE_PIN AE6 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[16]}]
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set_property -dict {PACKAGE_PIN AD5 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[17]}]
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set_property -dict {PACKAGE_PIN AD6 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[18]}]
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set_property -dict {PACKAGE_PIN AC6 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[19]}]
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set_property -dict {PACKAGE_PIN AE5 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[20]}]
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set_property -dict {PACKAGE_PIN AF3 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[21]}]
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set_property -dict {PACKAGE_PIN AE3 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[22]}]
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set_property -dict {PACKAGE_PIN AF2 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[23]}]
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set_property -dict {PACKAGE_PIN W3 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[24]}]
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set_property -dict {PACKAGE_PIN AF4 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[25]}]
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set_property -dict {PACKAGE_PIN AD4 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[26]}]
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set_property -dict {PACKAGE_PIN AF5 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[27]}]
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set_property -dict {PACKAGE_PIN Y1 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[28]}]
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set_property -dict {PACKAGE_PIN U7 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[29]}]
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set_property -dict {PACKAGE_PIN V2 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[30]}]
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set_property -dict {PACKAGE_PIN V1 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {GPIF_D[31]}]
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set_property -dict {PACKAGE_PIN AD1 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports IFCLK]
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set_property -dict {PACKAGE_PIN AB5 IOSTANDARD LVCMOS18} [get_ports FX3_EXTINT]
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# FX3 CTRL
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set_property -dict {PACKAGE_PIN AA4 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports GPIF_CTL0]
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set_property -dict {PACKAGE_PIN AE2 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports GPIF_CTL1]
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set_property -dict {PACKAGE_PIN AE1 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports GPIF_CTL2]
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set_property -dict {PACKAGE_PIN AC2 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports GPIF_CTL3]
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set_property -dict {PACKAGE_PIN AB6 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports GPIF_CTL4]
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set_property -dict {PACKAGE_PIN Y2 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports GPIF_CTL5]
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set_property -dict {PACKAGE_PIN AD3 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports GPIF_CTL6]
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set_property -dict {PACKAGE_PIN Y5 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports GPIF_CTL7]
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set_property -dict {PACKAGE_PIN AC3 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports GPIF_CTL8]
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set_property -dict {PACKAGE_PIN AB1 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports GPIF_CTL9]
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set_property -dict {PACKAGE_PIN AC4 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports GPIF_CTL11]
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set_property -dict {PACKAGE_PIN AB4 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports GPIF_CTL12]
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#debug uart
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set_property -dict {PACKAGE_PIN AD11 IOSTANDARD LVCMOS18} [get_ports FPGA_RXD0]
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set_property -dict {PACKAGE_PIN AE11 IOSTANDARD LVCMOS18} [get_ports FPGA_TXD0]
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#GPIO
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set_property -dict {PACKAGE_PIN AA13 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {fp_gpio[0]}]
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set_property -dict {PACKAGE_PIN AC13 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {fp_gpio[1]}]
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set_property -dict {PACKAGE_PIN AB12 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {fp_gpio[2]}]
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set_property -dict {PACKAGE_PIN AD13 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {fp_gpio[3]}]
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set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {fp_gpio[4]}]
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set_property -dict {PACKAGE_PIN AC12 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {fp_gpio[5]}]
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set_property -dict {PACKAGE_PIN AA12 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {fp_gpio[6]}]
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set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {fp_gpio[7]}]
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# LED
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set_property -dict {PACKAGE_PIN C11 IOSTANDARD LVCMOS33} [get_ports LED_TXRX1_RX]
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set_property -dict {PACKAGE_PIN E12 IOSTANDARD LVCMOS33} [get_ports LED_TXRX1_TX]
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set_property -dict {PACKAGE_PIN E13 IOSTANDARD LVCMOS33} [get_ports LED_RX1]
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set_property -dict {PACKAGE_PIN D10 IOSTANDARD LVCMOS33} [get_ports LED_RX2]
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set_property -dict {PACKAGE_PIN H13 IOSTANDARD LVCMOS33} [get_ports LED_TXRX2_RX]
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set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVCMOS33} [get_ports LED_TXRX2_TX]
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set_property -dict {PACKAGE_PIN B11 IOSTANDARD LVCMOS33} [get_ports LED_STATUS]
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set_property -dict {PACKAGE_PIN F9 IOSTANDARD LVCMOS33} [get_ports LED_CLK_G]
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set_property -dict {PACKAGE_PIN F8 IOSTANDARD LVCMOS33} [get_ports LED_CLK_R]
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# CAT
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set_property -dict {PACKAGE_PIN F23 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports codec_reset]
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set_property -dict {PACKAGE_PIN E23 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports codec_en_agc]
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set_property -dict {PACKAGE_PIN E22 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports codec_enable]
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set_property -dict {PACKAGE_PIN G24 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports codec_txrx]
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set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports codec_sync]
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set_property -dict {PACKAGE_PIN F22 IOSTANDARD LVCMOS18 SLEW SLOW PULLTYPE PULLUP } [get_ports cat_ce]
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set_property -dict {PACKAGE_PIN A20 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports cat_sclk]
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set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports cat_mosi]
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set_property -dict {PACKAGE_PIN G22 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports cat_miso]
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set_property -dict {PACKAGE_PIN F24 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports cat_clkout_fpga]
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# Control Lines
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set_property -dict {PACKAGE_PIN C22 IOSTANDARD LVCMOS18} [get_ports {codec_ctrl_out[0]}]
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set_property -dict {PACKAGE_PIN C26 IOSTANDARD LVCMOS18} [get_ports {codec_ctrl_out[1]}]
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set_property -dict {PACKAGE_PIN C24 IOSTANDARD LVCMOS18} [get_ports {codec_ctrl_out[2]}]
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set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS18} [get_ports {codec_ctrl_out[3]}]
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set_property -dict {PACKAGE_PIN C23 IOSTANDARD LVCMOS18} [get_ports {codec_ctrl_out[4]}]
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set_property -dict {PACKAGE_PIN D24 IOSTANDARD LVCMOS18} [get_ports {codec_ctrl_out[5]}]
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set_property -dict {PACKAGE_PIN D26 IOSTANDARD LVCMOS18} [get_ports {codec_ctrl_out[6]}]
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set_property -dict {PACKAGE_PIN D23 IOSTANDARD LVCMOS18} [get_ports {codec_ctrl_out[7]}]
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set_property -dict {PACKAGE_PIN A24 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {codec_ctrl_in[0]}]
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set_property -dict {PACKAGE_PIN B21 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {codec_ctrl_in[1]}]
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set_property -dict {PACKAGE_PIN C21 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {codec_ctrl_in[2]}]
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set_property -dict {PACKAGE_PIN A23 IOSTANDARD LVCMOS18 SLEW SLOW} [get_ports {codec_ctrl_in[3]}]
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# Tx Bus P0
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set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVCMOS18} [get_ports {tx_codec_d[0]}]
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set_property -dict {PACKAGE_PIN Y17 IOSTANDARD LVCMOS18} [get_ports {tx_codec_d[1]}]
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set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS18} [get_ports {tx_codec_d[2]}]
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set_property -dict {PACKAGE_PIN V16 IOSTANDARD LVCMOS18} [get_ports {tx_codec_d[3]}]
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set_property -dict {PACKAGE_PIN AA15 IOSTANDARD LVCMOS18} [get_ports {tx_codec_d[4]}]
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set_property -dict {PACKAGE_PIN AA14 IOSTANDARD LVCMOS18} [get_ports {tx_codec_d[5]}]
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set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS18} [get_ports {tx_codec_d[6]}]
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set_property -dict {PACKAGE_PIN W18 IOSTANDARD LVCMOS18} [get_ports {tx_codec_d[7]}]
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set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVCMOS18} [get_ports {tx_codec_d[8]}]
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set_property -dict {PACKAGE_PIN Y15 IOSTANDARD LVCMOS18} [get_ports {tx_codec_d[9]}]
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set_property -dict {PACKAGE_PIN AB20 IOSTANDARD LVCMOS18} [get_ports {tx_codec_d[10]}]
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set_property -dict {PACKAGE_PIN AB19 IOSTANDARD LVCMOS18} [get_ports {tx_codec_d[11]}]
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# RX Bus P1
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set_property -dict {PACKAGE_PIN AF20 IOSTANDARD LVCMOS18} [get_ports {rx_codec_d[0]}]
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set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVCMOS18} [get_ports {rx_codec_d[1]}]
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set_property -dict {PACKAGE_PIN AE20 IOSTANDARD LVCMOS18} [get_ports {rx_codec_d[2]}]
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set_property -dict {PACKAGE_PIN AD20 IOSTANDARD LVCMOS18} [get_ports {rx_codec_d[3]}]
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set_property -dict {PACKAGE_PIN AE16 IOSTANDARD LVCMOS18} [get_ports {rx_codec_d[4]}]
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set_property -dict {PACKAGE_PIN AD16 IOSTANDARD LVCMOS18} [get_ports {rx_codec_d[5]}]
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set_property -dict {PACKAGE_PIN AB15 IOSTANDARD LVCMOS18} [get_ports {rx_codec_d[6]}]
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set_property -dict {PACKAGE_PIN AB14 IOSTANDARD LVCMOS18} [get_ports {rx_codec_d[7]}]
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set_property -dict {PACKAGE_PIN AD14 IOSTANDARD LVCMOS18} [get_ports {rx_codec_d[8]}]
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set_property -dict {PACKAGE_PIN AC14 IOSTANDARD LVCMOS18} [get_ports {rx_codec_d[9]}]
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set_property -dict {PACKAGE_PIN AD19 IOSTANDARD LVCMOS18} [get_ports {rx_codec_d[10]}]
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set_property -dict {PACKAGE_PIN AC19 IOSTANDARD LVCMOS18} [get_ports {rx_codec_d[11]}]
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# Frame syncs
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set_property -dict {PACKAGE_PIN AB16 IOSTANDARD LVCMOS18} [get_ports codec_data_clk_p]
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set_property -dict {PACKAGE_PIN AA19 IOSTANDARD LVCMOS18} [get_ports rx_frame_p]
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set_property -dict {PACKAGE_PIN AB17 IOSTANDARD LVCMOS18} [get_ports tx_frame_p]
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set_property -dict {PACKAGE_PIN AC18 IOSTANDARD LVCMOS18} [get_ports codec_fb_clk_p]
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## RF Hardware Control
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set_property -dict {PACKAGE_PIN A15 IOSTANDARD LVCMOS33} [get_ports SFDX1_RX]
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set_property -dict {PACKAGE_PIN B12 IOSTANDARD LVCMOS33} [get_ports SFDX1_TX]
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set_property -dict {PACKAGE_PIN B10 IOSTANDARD LVCMOS33} [get_ports SFDX2_RX]
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set_property -dict {PACKAGE_PIN H11 IOSTANDARD LVCMOS33} [get_ports SFDX2_TX]
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set_property -dict {PACKAGE_PIN A13 IOSTANDARD LVCMOS33} [get_ports SRX1_RX]
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set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS33} [get_ports SRX1_TX]
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set_property -dict {PACKAGE_PIN A10 IOSTANDARD LVCMOS33} [get_ports SRX2_RX]
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set_property -dict {PACKAGE_PIN G10 IOSTANDARD LVCMOS33} [get_ports SRX2_TX]
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set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS33} [get_ports tx_bandsel_a]
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set_property -dict {PACKAGE_PIN G12 IOSTANDARD LVCMOS33} [get_ports tx_bandsel_b]
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set_property -dict {PACKAGE_PIN F14 IOSTANDARD LVCMOS33} [get_ports rx_bandsel_a]
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set_property -dict {PACKAGE_PIN F12 IOSTANDARD LVCMOS33} [get_ports rx_bandsel_b]
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set_property -dict {PACKAGE_PIN F13 IOSTANDARD LVCMOS33} [get_ports rx_bandsel_c]
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set_property -dict {PACKAGE_PIN D13 IOSTANDARD LVCMOS33} [get_ports tx_enable1]
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set_property -dict {PACKAGE_PIN J10 IOSTANDARD LVCMOS33} [get_ports tx_enable2]
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# IFCLK is 100 MHz GPIF clock
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create_clock -period 10.000 -name IFCLK [get_ports IFCLK]
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create_clock -period 16.276 -name codec_data_clk_p [get_ports codec_data_clk_p]
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# --------------------------------------------------------------------------
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# Radio clock BUFGMUX modes
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#
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# Vivado 2026.1 inferred these constraints with:
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# write_inferred_xdc -excl_clocks
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#
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# The radio clock tree can run from either:
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# I0 = codec_data_clk_p (full-rate / SISO)
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# I1 = rx_clk_mimo_bufr (divide-by-2 / MIMO)
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#
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# These two modes are mutually exclusive only downstream of BUFGMUX_inst.
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# Keep their upstream interaction intact.
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# --------------------------------------------------------------------------
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create_generated_clock \
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-name codec_data_clk_p_Gen \
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-source [get_pins b200_io_i0/BUFGMUX_inst/I0] \
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-add \
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-master_clock codec_data_clk_p \
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-divide_by 1 \
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[get_pins b200_io_i0/BUFGMUX_inst/O]
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create_generated_clock \
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-name rx_clk_mimo_bufr_Gen \
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-source [get_pins b200_io_i0/BUFGMUX_inst/I1] \
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-add \
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-master_clock [get_clocks -of [get_pins b200_io_i0/BUFGMUX_inst/I1] -filter {IS_GENERATED}] \
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-divide_by 1 \
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[get_pins b200_io_i0/BUFGMUX_inst/O]
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set_clock_groups \
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-logically_exclusive \
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-group [get_clocks -include_generated_clocks {codec_data_clk_p_Gen}] \
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-group [get_clocks -include_generated_clocks {rx_clk_mimo_bufr_Gen}]
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# --------------------------------------------------------------------------
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# GPIF <-> radio domains are asynchronous.
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#
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# Bound physical datapath delay without imposing an unrelated clock-phase
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# relationship. More-specific XPM FIFO constraints remain in effect.
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# --------------------------------------------------------------------------
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set gpif_clk \
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[get_clocks -of_objects \
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[get_pins gen_clks/inst/mmcm_adv_inst/CLKOUT1]]
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set_max_delay 10.000 \
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-datapath_only \
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-from $gpif_clk \
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-to [get_clocks {codec_data_clk_p_Gen rx_clk_mimo_bufr_Gen}]
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set_max_delay 10.000 \
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-datapath_only \
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-from [get_clocks {codec_data_clk_p_Gen rx_clk_mimo_bufr_Gen}] \
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-to $gpif_clk
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set_false_path -from [get_clocks -of_objects [get_pins gen_clks/inst/mmcm_adv_inst/CLKOUT1]] -to [get_clocks codec_data_clk_p]
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set_false_path -from [get_clocks -of_objects [get_pins gen_clks/inst/mmcm_adv_inst/CLKOUT1]] -to [get_clocks -of_objects [get_pins b200_io_i0/BUFR_inst/O]]
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set_false_path -from [get_clocks codec_data_clk_p] -to [get_clocks -of_objects [get_pins gen_clks/inst/mmcm_adv_inst/CLKOUT1]]
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set_false_path -from [get_clocks -of_objects [get_pins b200_io_i0/BUFR_inst/O]] -to [get_clocks -of_objects [get_pins gen_clks/inst/mmcm_adv_inst/CLKOUT1]]
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
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