Martin Braun
df0b86f432
This removes a duplicate code section that causes build warnings. It also references a wire that gets declared further down and the removed and remaining code sections were incorrectly indented. Original-commit: e8084eb4cb4ec6ff6476feb6e77ab3ea45dd969e
499 lines
18 KiB
Verilog
499 lines
18 KiB
Verilog
//
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// Copyright 2016-2017 Ettus Research LLC
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// Copyright 2017 Ettus Research, a National Instruments Company
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// sfpp_io_core
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// - mdio_master
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// - One Gige phy + MAC
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// - Ten Gige phy + MAC
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// - Aurora phy + MAC
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//
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//////////////////////////////////////////////////////////////////////
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module x300_sfpp_io_core #(
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parameter PROTOCOL = "10GbE", // Must be {10GbE, 1GbE, Aurora}
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parameter PORTNUM = 8'd0
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)(
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input areset,
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input bus_rst,
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input bus_rst_div2,
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input gt_refclk,
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input gb_refclk,
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input misc_clk,
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input bus_clk,
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input bus_clk_div2,
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output txp,
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output txn,
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input rxp,
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input rxn,
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input sfpp_rxlos,
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input sfpp_tx_fault,
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output sfpp_tx_disable,
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input [63:0] s_axis_tdata,
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input [3:0] s_axis_tuser,
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input s_axis_tlast,
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input s_axis_tvalid,
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output s_axis_tready,
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output [63:0] m_axis_tdata,
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output [3:0] m_axis_tuser,
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output m_axis_tlast,
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output m_axis_tvalid,
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input m_axis_tready,
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input [7:0] wb_adr_i,
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input wb_cyc_i,
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input [31:0] wb_dat_i,
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input wb_stb_i,
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input wb_we_i,
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output wb_ack_o,
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output [31:0] wb_dat_o,
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output wb_int_o,
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output [15:0] phy_status,
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output link_up,
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output activity
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);
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wire mdc, mdio_in, mdio_out;
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// Flush logic: If the link is not up, we will flush all packets coming from
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// the device. This avoids the MAC backpressuring when the PHY is down.
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// The device will always send discovery packets to the transports during
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// initialization, and they have no way of knowing if it's safe to travel
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// down this route. c2mac == "CHDR to MAC"
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wire [63:0] c2mac_tdata;
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wire [3:0] c2mac_tuser;
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wire c2mac_tlast;
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wire c2mac_tvalid;
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wire c2mac_tready;
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axis_packet_flush #(
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.WIDTH(64+4), // tdata + tuser
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.TIMEOUT_W(1), // Not using timeout
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.FLUSH_PARTIAL_PKTS(0),
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.PIPELINE("NONE")
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) linkup_flush (
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.clk(bus_clk),
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.reset(bus_rst),
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.enable(~link_up), // enable flushing when link down
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.timeout(1'b0),
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.flushing(/* not required */),
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.done(/* not required */),
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// Input from device/crossbar
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.s_axis_tdata ({s_axis_tuser, s_axis_tdata}),
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.s_axis_tlast (s_axis_tlast),
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.s_axis_tvalid (s_axis_tvalid),
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.s_axis_tready (s_axis_tready),
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// Output to MAC
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.m_axis_tdata ({c2mac_tuser, c2mac_tdata}),
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.m_axis_tlast (c2mac_tlast),
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.m_axis_tvalid (c2mac_tvalid),
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.m_axis_tready (c2mac_tready)
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);
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generate
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if (PROTOCOL == "10GbE") begin
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//-----------------------------------------------------------------
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// 10 Gigabit Ethernet
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//-----------------------------------------------------------------
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wire [63:0] xgmii_txd;
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wire [7:0] xgmii_txc;
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wire [63:0] xgmii_rxd;
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wire [7:0] xgmii_rxc;
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wire [7:0] xgmii_status;
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wire xge_phy_resetdone;
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ten_gige_phy ten_gige_phy_i
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(
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// Clocks and Reset
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.areset(areset), // Asynchronous reset for entire core.
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.refclk(gt_refclk), // Transciever reference clock: 156.25MHz
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.clk156(gb_refclk), // Globally buffered core clock: 156.25MHz
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.dclk(misc_clk), // Management/DRP clock: 78.125MHz
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.sim_speedup_control(1'b0),
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// GMII Interface (client MAC <=> PCS)
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.xgmii_txd(xgmii_txd), // Transmit data from client MAC.
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.xgmii_txc(xgmii_txc), // Transmit control signal from client MAC.
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.xgmii_rxd(xgmii_rxd), // Received Data to client MAC.
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.xgmii_rxc(xgmii_rxc), // Received control signal to client MAC.
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// Tranceiver Interface
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.txp(txp), // Differential +ve of serial transmission from PMA to PMD.
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.txn(txn), // Differential -ve of serial transmission from PMA to PMD.
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.rxp(rxp), // Differential +ve for serial reception from PMD to PMA.
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.rxn(rxn), // Differential -ve for serial reception from PMD to PMA.
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// Management: MDIO Interface
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.mdc(mdc), // Management Data Clock
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.mdio_in(mdio_in), // Management Data In
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.mdio_out(mdio_out), // Management Data Out
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.mdio_tri(), // Management Data Tristate
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.prtad(5'd4), // MDIO address is 4
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// General IO's
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.core_status(xgmii_status), // Core status
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.resetdone(xge_phy_resetdone),
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.signal_detect(~sfpp_rxlos), // Input from PMD to indicate presence of optical input. (Undocumented, but it seems Xilinx expect this to be inverted.)
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.tx_fault(sfpp_tx_fault),
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.tx_disable(sfpp_tx_disable)
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);
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xge_mac_wrapper #(
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.PORTNUM(PORTNUM),
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.WISHBONE(1)
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) xge_mac_wrapper_i (
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// XGMII
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.xgmii_clk(gb_refclk),
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.xgmii_txd(xgmii_txd),
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.xgmii_txc(xgmii_txc),
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.xgmii_rxd(xgmii_rxd),
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.xgmii_rxc(xgmii_rxc),
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// MDIO
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.mdc(mdc),
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.mdio_in(mdio_in),
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.mdio_out(mdio_out),
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// Wishbone I/F
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.wb_clk_i(bus_clk_div2),
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.wb_rst_i(bus_rst_div2),
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.wb_adr_i(wb_adr_i),
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.wb_cyc_i(wb_cyc_i),
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.wb_dat_i(wb_dat_i),
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.wb_stb_i(wb_stb_i),
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.wb_we_i(wb_we_i),
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.wb_ack_o(wb_ack_o),
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.wb_dat_o(wb_dat_o),
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.wb_int_o(wb_int_o),
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// Client FIFO Interfaces
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.sys_clk(bus_clk),
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.sys_rst(bus_rst),
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.rx_tdata(m_axis_tdata),
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.rx_tuser(m_axis_tuser),
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.rx_tlast(m_axis_tlast),
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.rx_tvalid(m_axis_tvalid),
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.rx_tready(m_axis_tready),
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.tx_tdata(c2mac_tdata),
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.tx_tuser(c2mac_tuser), // Bit[3] (error) is ignored for now.
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.tx_tlast(c2mac_tlast),
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.tx_tvalid(c2mac_tvalid),
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.tx_tready(c2mac_tready),
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// Other
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.phy_ready(xge_phy_resetdone)
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);
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assign phy_status = {8'h00, xgmii_status};
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// Use the PCS Block Lock signal to drive the link_up LED on the FP.
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// For further details, see Xilinx' PG068, Table 2-11 (core_status[0] signal).
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synchronizer #(.INITIAL_VAL(1'b0)) link_up_sync (
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.clk(bus_clk), .rst(1'b0 /* no reset */), .in(xgmii_status[0]), .out(link_up));
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end else if (PROTOCOL == "1GbE") begin
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//-----------------------------------------------------------------
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// 1 Gigabit Ethernet
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//-----------------------------------------------------------------
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wire [7:0] gmii_txd, gmii_rxd;
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wire gmii_tx_en, gmii_tx_er, gmii_rx_dv, gmii_rx_er;
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wire gmii_clk;
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assign sfpp_tx_disable = 1'b0; // Always on.
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one_gige_phy one_gige_phy_i
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(
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.reset(areset), // Asynchronous reset for entire core.
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.independent_clock(bus_clk),
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// Tranceiver Interface
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.gtrefclk(gt_refclk), // Reference clock for MGT: 125MHz, very high quality.
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.gtrefclk_bufg(gb_refclk), // Reference clock routed through a BUFG
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.txp(txp), // Differential +ve of serial transmission from PMA to PMD.
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.txn(txn), // Differential -ve of serial transmission from PMA to PMD.
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.rxp(rxp), // Differential +ve for serial reception from PMD to PMA.
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.rxn(rxn), // Differential -ve for serial reception from PMD to PMA.
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// GMII Interface (client MAC <=> PCS)
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.gmii_clk(gmii_clk), // Clock to client MAC.
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.gmii_txd(gmii_txd), // Transmit data from client MAC.
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.gmii_tx_en(gmii_tx_en), // Transmit control signal from client MAC.
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.gmii_tx_er(gmii_tx_er), // Transmit control signal from client MAC.
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.gmii_rxd(gmii_rxd), // Received Data to client MAC.
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.gmii_rx_dv(gmii_rx_dv), // Received control signal to client MAC.
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.gmii_rx_er(gmii_rx_er), // Received control signal to client MAC.
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// Management: MDIO Interface
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.mdc(mdc), // Management Data Clock
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.mdio_i(mdio_in), // Management Data In
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.mdio_o(mdio_out), // Management Data Out
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.mdio_t(), // Management Data Tristate
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.configuration_vector(5'd0), // Alternative to MDIO interface.
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.configuration_valid(1'b1), // Validation signal for Config vector (MUST be 1 for proper functionality...undocumented)
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// General IO's
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.status_vector(phy_status), // Core status.
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.signal_detect(1'b1 /*Optical module not supported*/) // Input from PMD to indicate presence of optical input.
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);
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simple_gemac_wrapper #(.RX_FLOW_CTRL(0), .PORTNUM(PORTNUM)) simple_gemac_wrapper_i
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(
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.clk125(gmii_clk),
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.reset(areset),
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.GMII_GTX_CLK(),
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.GMII_TX_EN(gmii_tx_en),
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.GMII_TX_ER(gmii_tx_er),
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.GMII_TXD(gmii_txd),
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.GMII_RX_CLK(gmii_clk),
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.GMII_RX_DV(gmii_rx_dv),
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.GMII_RX_ER(gmii_rx_er),
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.GMII_RXD(gmii_rxd),
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.sys_clk(bus_clk),
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.rx_tdata(m_axis_tdata),
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.rx_tuser(m_axis_tuser),
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.rx_tlast(m_axis_tlast),
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.rx_tvalid(m_axis_tvalid),
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.rx_tready(m_axis_tready),
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.tx_tdata(c2mac_tdata),
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.tx_tuser(c2mac_tuser),
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.tx_tlast(c2mac_tlast),
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.tx_tvalid(c2mac_tvalid),
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.tx_tready(c2mac_tready),
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// MDIO
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.mdc(mdc),
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.mdio_in(mdio_in),
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.mdio_out(mdio_out),
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.mdio_tri(),
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// Wishbone I/F
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.wb_clk_i(bus_clk_div2),
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.wb_rst_i(bus_rst_div2),
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.wb_adr_i(wb_adr_i),
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.wb_cyc_i(wb_cyc_i),
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.wb_dat_i(wb_dat_o),
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.wb_stb_i(wb_stb_i),
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.wb_we_i(wb_we_i),
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.wb_ack_o(wb_ack_o),
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.wb_dat_o(wb_dat_i),
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.wb_int_o(wb_int_o),
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// Debug
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.debug_tx(), .debug_rx()
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);
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// Use the Link Status signal to drive the link_up LED on the FP.
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// For further details, see Xilinx' PG047, Table 2-76 (status_vector[0]).
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synchronizer #(.INITIAL_VAL(1'b0)) link_up_sync (
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.clk(bus_clk), .rst(1'b0 /* no reset */), .in(phy_status[0]), .out(link_up));
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end else if (PROTOCOL == "Aurora") begin
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//-----------------------------------------------------------------
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// Aurora
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//-----------------------------------------------------------------
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wire au_user_clk, au_user_rst, phy_areset;
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wire [63:0] i_tdata, o_tdata;
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wire i_tvalid, i_tready, o_tvalid;
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wire channel_up, hard_err, soft_err;
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wire mac_clear;
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assign sfpp_tx_disable = 1'b0; // Always on.
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aurora_phy_x1 aurora_phy_i (
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// Resets
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.areset(areset | phy_areset),
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// Clocks
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.refclk(gt_refclk),
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.init_clk(misc_clk),
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.user_clk(au_user_clk),
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.user_rst(au_user_rst),
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// GTX Serial I/O
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.tx_p(txp),
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.tx_n(txn),
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.rx_p(rxp),
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.rx_n(rxn),
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// AXI4-Stream TX Interface
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.s_axis_tdata(i_tdata),
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.s_axis_tvalid(i_tvalid),
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.s_axis_tready(i_tready),
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// AXI4-Stream RX Interface
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.m_axis_tdata(o_tdata),
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.m_axis_tvalid(o_tvalid),
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// AXI4-Lite Config Interface: TODO: Hook up to WB->AXI4Lite converter
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.s_axi_awaddr(32'h0),
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.s_axi_araddr(32'h0),
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.s_axi_awvalid(1'b0),
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.s_axi_awready(),
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.s_axi_wdata(32'h0),
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.s_axi_wvalid(1'b0),
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.s_axi_wstrb(1'b0),
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.s_axi_wready(),
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.s_axi_bvalid(),
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.s_axi_bresp(),
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.s_axi_bready(1'b1),
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.s_axi_arready(),
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.s_axi_arvalid(1'b0),
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.s_axi_rdata(),
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.s_axi_rvalid(),
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.s_axi_rresp(),
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.s_axi_rready(1'b1),
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// Status and Error Reporting Interface
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.channel_up(channel_up),
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.hard_err(hard_err),
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.soft_err(soft_err)
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);
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assign phy_status = {14'd0, hard_err, channel_up};
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wire bist_gen_en, bist_checker_en, bist_loopback_en;
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wire bist_checker_locked;
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wire [5:0] bist_gen_rate;
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wire [47:0] bist_checker_samps, bist_checker_errors;
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wire [31:0] overruns, checksum_errors;
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aurora_axis_mac #(
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.PHY_ENDIANNESS ("LITTLE"),
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.PACKET_MODE (1),
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.MAX_PACKET_SIZE(1024),
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.BIST_ENABLED (1)
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) aurora_mac_i (
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// Clocks and resets
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.phy_clk(au_user_clk), .phy_rst(au_user_rst),
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.sys_clk(bus_clk), .sys_rst(bus_rst),
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.clear(mac_clear),
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// PHY Interface (Synchronous to phy_clk)
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.phy_s_axis_tdata(o_tdata),
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.phy_s_axis_tvalid(o_tvalid),
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.phy_m_axis_tdata(i_tdata),
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.phy_m_axis_tvalid(i_tvalid),
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.phy_m_axis_tready(i_tready),
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// User Interface (Synchronous to sys_clk)
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.s_axis_tdata(c2mac_tdata),
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.s_axis_tlast(c2mac_tlast),
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.s_axis_tvalid(c2mac_tvalid),
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.s_axis_tready(c2mac_tready),
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.m_axis_tdata(m_axis_tdata),
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.m_axis_tlast(m_axis_tlast),
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.m_axis_tvalid(m_axis_tvalid),
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.m_axis_tready(m_axis_tready),
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// PHY Status Inputs (Synchronous to phy_clk)
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.channel_up(channel_up),
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.hard_err(hard_err),
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.soft_err(soft_err),
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// Status and Error Outputs (Synchronous to sys_clk)
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.overruns(overruns),
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.soft_errors(),
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.checksum_errors(checksum_errors),
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.critical_err(mac_crit_err),
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// BIST Interface (Synchronous to sys_clk)
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.bist_gen_en(bist_gen_en),
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.bist_gen_rate(bist_gen_rate),
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.bist_checker_en(bist_checker_en),
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.bist_loopback_en(bist_loopback_en),
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.bist_checker_locked(bist_checker_locked),
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.bist_checker_samps(bist_checker_samps),
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.bist_checker_errors(bist_checker_errors)
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);
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assign m_axis_tuser = 4'd0;
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wire set_stb;
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wire [3:0] set_addr, rb_addr;
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wire [31:0] set_data;
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reg [31:0] rb_data;
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settings_bus #(.AWIDTH(8), .DWIDTH(32), .SWIDTH(4)) settings_bus_i (
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.wb_clk(bus_clk), .wb_rst(bus_rst),
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.wb_adr_i(wb_adr_i), .wb_dat_i(wb_dat_i),
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.wb_stb_i(wb_stb_i), .wb_we_i(wb_we_i), .wb_ack_o(wb_ack_o),
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.strobe(set_stb), .addr(set_addr), .data(set_data)
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);
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settings_readback #(.AWIDTH(8),.DWIDTH(32), .RB_ADDRW(4)) settings_readback_i (
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.wb_clk(bus_clk), .wb_rst(bus_rst),
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.wb_adr_i(wb_adr_i), .wb_stb_i(wb_stb_i), .wb_we_i(wb_we_i), .wb_dat_o(wb_dat_o),
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.rb_data(rb_data), .rb_addr(rb_addr), .rb_rd_stb()
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);
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setting_reg #(.my_addr(4'd0), .awidth(4), .width(11), .at_reset(11'h000)) set_core_control_i (
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.clk(bus_clk), .rst(bus_rst),
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.strobe(set_stb), .addr(set_addr), .in(set_data),
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.out({mac_clear, phy_areset, bist_gen_rate, bist_loopback_en, bist_gen_en, bist_checker_en}), .changed()
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);
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|
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wire channel_up_bclk, hard_err_bclk, soft_err_bclk, mac_crit_err_bclk;
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synchronizer #(.INITIAL_VAL(1'b0)) channel_up_sync (
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.clk(bus_clk), .rst(1'b0 /* no reset */), .in(channel_up), .out(channel_up_bclk));
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synchronizer #(.INITIAL_VAL(1'b0)) hard_err_sync (
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.clk(bus_clk), .rst(1'b0 /* no reset */), .in(hard_err), .out(hard_err_bclk));
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synchronizer #(.INITIAL_VAL(1'b0)) soft_err_sync (
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.clk(bus_clk), .rst(1'b0 /* no reset */), .in(soft_err), .out(soft_err_bclk));
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synchronizer #(.INITIAL_VAL(1'b0)) mac_crit_err_sync (
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|
.clk(bus_clk), .rst(1'b0 /* no reset */), .in(mac_crit_err), .out(mac_crit_err_bclk));
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|
|
|
reg [19:0] bist_lock_latency;
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|
always @(posedge bus_clk) begin
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|
if (!bist_checker_en && !bist_checker_locked)
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bist_lock_latency <= 20'd0;
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else if (bist_checker_en && !bist_checker_locked)
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bist_lock_latency <= bist_lock_latency + 20'd1;
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|
end
|
|
|
|
reg mac_crit_err_latch;
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|
always @(posedge bus_clk) begin
|
|
if (bus_rst | mac_clear) begin
|
|
mac_crit_err_latch <= 1'b0;
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|
end else begin
|
|
if (mac_crit_err_bclk)
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|
mac_crit_err_latch <= 1'b1;
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|
end
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|
end
|
|
|
|
wire [31:0] core_status = {
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6'h0, //[31:26]
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|
mac_crit_err_latch, //[25]
|
|
1, //[24] mmcm_locked_bclk
|
|
1, //[23] gt_pll_locked_bclk
|
|
0, //[22] qpll_refclklost_bclk
|
|
1, //[21] qpll_lock_bclk
|
|
0, //[20] qpll_reset_bclk
|
|
bist_lock_latency[19:4], //[19:4]
|
|
bist_checker_locked, //[3]
|
|
soft_err_bclk, //[2]
|
|
hard_err_bclk, //[1]
|
|
channel_up_bclk //[0]
|
|
};
|
|
|
|
assign link_up = channel_up_bclk;
|
|
|
|
always @(*)
|
|
case (rb_addr)
|
|
4'd0: rb_data = core_status;
|
|
4'd1: rb_data = overruns;
|
|
4'd2: rb_data = checksum_errors;
|
|
4'd3: rb_data = bist_checker_samps[47:16]; //Scale num sample by 2^16
|
|
4'd4: rb_data = bist_checker_errors[31:0]; //Dont scale errors
|
|
default: rb_data = 32'h0;
|
|
endcase // case (rb_addr)
|
|
|
|
end else begin
|
|
|
|
//Invalid protocol
|
|
|
|
end
|
|
endgenerate
|
|
|
|
//-----------------------------------------------------------------
|
|
// Activity detector
|
|
//-----------------------------------------------------------------
|
|
|
|
pulse_stretch act_pulse_str_i (
|
|
.clk(bus_clk),
|
|
.rst(bus_rst | ~link_up),
|
|
.pulse((s_axis_tvalid & s_axis_tready) | (m_axis_tvalid & m_axis_tready)),
|
|
.pulse_stretched(activity)
|
|
);
|
|
|
|
endmodule
|
|
|