196 lines
7.3 KiB
Verilog
196 lines
7.3 KiB
Verilog
//
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// Copyright 2021 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: axis_switch
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//
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// Description:
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//
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// Implementation of a M-input, N-output AXI-Stream switch. One of the M
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// input ports is allocated based on the s_axis_alloc signal and the packet
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// on that port is sent to one of the N output ports based on the tdest
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// signal.
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//
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// Parameters:
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//
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// DATA_W : tdata width
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// DEST_W : Output tdest width
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// IN_PORTS : Number of input ports
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// OUT_PORTS : Number of output ports
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// PIPELINE : Instantiate output pipeline stage?
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// ALLOC_W : PRIVATE. Do not modify.
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//
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// Ports:
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//
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// clk : Switch clock
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// reset : Reset
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// s_axis_tdata : Input data
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// s_axis_tdest : Input destination
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// s_axis_tlast : Input EOP (last)
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// s_axis_tvalid : Input valid
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// s_axis_tready : Input ready
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// s_axis_alloc : Input port allocation for switch
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// m_axis_tdata : Output data
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// m_axis_tdest : Output destination
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// m_axis_tlast : Output EOP (last)
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// m_axis_tvalid : Output valid
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// m_axis_tready : Output ready
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//
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`default_nettype none
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module axis_switch #(
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parameter DATA_W = 64,
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parameter DEST_W = 1,
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parameter IN_PORTS = 3,
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parameter OUT_PORTS = 3,
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parameter PIPELINE = 1,
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parameter ALLOC_W = (IN_PORTS == 1) ? 1 : $clog2(IN_PORTS)
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) (
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// Clocks and resets
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input wire clk,
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input wire reset,
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// Input ports
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input wire [(DATA_W*IN_PORTS)-1:0] s_axis_tdata,
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input wire [((DEST_W+$clog2(OUT_PORTS))*IN_PORTS)-1:0] s_axis_tdest,
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input wire [IN_PORTS-1:0] s_axis_tlast,
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input wire [IN_PORTS-1:0] s_axis_tvalid,
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output wire [IN_PORTS-1:0] s_axis_tready,
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input wire [ALLOC_W-1:0] s_axis_alloc,
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// Output ports
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output wire [(DATA_W*OUT_PORTS)-1:0] m_axis_tdata,
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output wire [(DEST_W*OUT_PORTS)-1:0] m_axis_tdest,
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output wire [OUT_PORTS-1:0] m_axis_tlast,
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output wire [OUT_PORTS-1:0] m_axis_tvalid,
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input wire [OUT_PORTS-1:0] m_axis_tready
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);
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localparam CLOG2_OUT_PORTS = $clog2(OUT_PORTS);
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//---------------------------------------------------------
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// Flatten/unflatten and pipeline
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//---------------------------------------------------------
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wire [DATA_W-1:0] i_tdata [0:IN_PORTS-1];
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wire [DEST_W+$clog2(OUT_PORTS)-1:0] i_tdest [0:IN_PORTS-1];
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wire i_tlast [0:IN_PORTS-1];
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wire [IN_PORTS-1:0] i_tvalid;
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wire [IN_PORTS-1:0] i_tready;
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wire [ALLOC_W-1:0] i_alloc;
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wire [DATA_W-1:0] o_tdata [0:OUT_PORTS-1];
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wire [DEST_W-1:0] o_tdest [0:OUT_PORTS-1];
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wire o_tlast [0:OUT_PORTS-1];
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wire [OUT_PORTS-1:0] o_tvalid;
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wire [OUT_PORTS-1:0] o_tready;
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genvar i, o;
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generate
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for (i = 0; i < IN_PORTS; i = i + 1) begin: in_ports
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assign i_tdata [i] = s_axis_tdata [(i*DATA_W)+:DATA_W];
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assign i_tdest [i] = s_axis_tdest [(i*(DEST_W+CLOG2_OUT_PORTS))+:(DEST_W+CLOG2_OUT_PORTS)];
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assign i_tlast [i] = s_axis_tlast [i];
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assign i_tvalid [i] = s_axis_tvalid[i];
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assign s_axis_tready[i] = i_tready [i];
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end
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assign i_alloc = s_axis_alloc; // i_alloc has to be delay-matched to valid
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for (o = 0; o < OUT_PORTS; o = o + 1) begin : gen_for_pipeline
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if (PIPELINE == 1) begin : gen_pipeline
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axi_fifo_flop2 #(.WIDTH(DEST_W+1+DATA_W)) axi_fifo_flop2_i (
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.clk(clk), .reset(reset), .clear(1'b0),
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.i_tdata({o_tdest[o], o_tlast[o], o_tdata[o]}),
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.i_tvalid(o_tvalid[o]), .i_tready(o_tready[o]),
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.o_tdata({m_axis_tdest[(o*DEST_W)+:DEST_W], m_axis_tlast[o], m_axis_tdata[(o*DATA_W)+:DATA_W]}),
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.o_tvalid(m_axis_tvalid[o]), .o_tready(m_axis_tready[o]),
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.space(), .occupied()
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);
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end else begin : gen_no_pipeline
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assign m_axis_tdata [(o*DATA_W)+:DATA_W] = o_tdata [o];
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assign m_axis_tdest [(o*DEST_W)+:DEST_W] = o_tdest [o];
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assign m_axis_tlast [o] = o_tlast [o];
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assign m_axis_tvalid[o] = o_tvalid [o];
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assign o_tready [o] = m_axis_tready[o];
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end
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end
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endgenerate
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//---------------------------------------------------------
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// Allocator
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//---------------------------------------------------------
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// The "chosen" input port will drive this bus
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wire [DATA_W-1:0] master_tdata;
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wire [DEST_W+$clog2(OUT_PORTS)-1:0] master_tdest;
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wire master_tlast;
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wire master_tvalid;
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wire master_tready;
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generate if (IN_PORTS > 1) begin : gen_mult_in_ports
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reg [IN_PORTS-1:0] ialloc_oh;
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reg [$clog2(IN_PORTS)-1:0] alloc_reg;
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always @(posedge clk) begin
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if (reset) begin
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ialloc_oh <= {IN_PORTS{1'b0}};
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end else begin
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if (ialloc_oh == {IN_PORTS{1'b0}}) begin
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if (|i_tvalid) begin
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ialloc_oh[i_alloc] <= 1'b1;
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alloc_reg <= i_alloc;
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end
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end else begin
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if(master_tready & master_tvalid & master_tlast)
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ialloc_oh <= {IN_PORTS{1'b0}};
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end
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end
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end
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assign master_tdata = i_tdata[alloc_reg];
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assign master_tdest = i_tdest[alloc_reg];
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assign master_tlast = i_tlast[alloc_reg];
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assign master_tvalid = |(i_tvalid & ialloc_oh);
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assign i_tready = i_tvalid & ialloc_oh & {IN_PORTS{master_tready}};
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end else begin : gen_single_in_port
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// Special case: One input port
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assign master_tdata = i_tdata[0];
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assign master_tdest = i_tdest[0];
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assign master_tlast = i_tlast[0];
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assign master_tvalid = i_tvalid[0];
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assign i_tready[0] = master_tready;
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end endgenerate
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//---------------------------------------------------------
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// Router
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//---------------------------------------------------------
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generate if (OUT_PORTS > 1) begin : gen_mult_out_ports
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reg [OUT_PORTS-1:0] odst_oh;
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always @(posedge clk) begin
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if (reset) begin
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odst_oh <= {OUT_PORTS{1'b0}};
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end else begin
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if (odst_oh == {OUT_PORTS{1'b0}}) begin
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if (master_tvalid)
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odst_oh[master_tdest[CLOG2_OUT_PORTS-1:0]] <= 1'b1;
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end else begin
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if(master_tready & master_tvalid & master_tlast)
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odst_oh <= {OUT_PORTS{1'b0}};
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end
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end
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end
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assign master_tready = |(o_tready & odst_oh);
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assign o_tvalid = {OUT_PORTS{master_tvalid}} & odst_oh;
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end else begin : gen_single_out_port
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// Special case: One output port
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assign master_tready = o_tready[0];
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assign o_tvalid[0] = master_tvalid;
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end endgenerate
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generate for (o = 0; o < OUT_PORTS; o = o + 1) begin : gen_outputs
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assign o_tdata[o] = master_tdata;
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assign o_tdest[o] = master_tdest[DEST_W+CLOG2_OUT_PORTS-1:CLOG2_OUT_PORTS];
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assign o_tlast[o] = master_tlast;
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end endgenerate
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endmodule
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`default_nettype wire
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