miegl
90e0b1d038
Use the real axi_fifo_2clk hierarchy with XPM-based asynchronous FIFO implementations instead of synthesizing axi_fifo_2clk_sim. Map the deep stream FIFOs into dedicated block RAM while preserving the legacy FWFT FIFO interface.
45 lines
1.1 KiB
Verilog
45 lines
1.1 KiB
Verilog
// SPDX-License-Identifier: LGPL-3.0-or-later
|
|
// Drop-in replacement for Ettus/X300 fifo_4k_2clk FIFO Generator IP.
|
|
// X300 configuration: 72 bits x 512 words (36 Kibit), independent clocks,
|
|
// block RAM, FWFT, 2 CDC synchronization stages.
|
|
|
|
`timescale 1ns/1ps
|
|
`default_nettype none
|
|
|
|
module fifo_4k_2clk (
|
|
input wire rst,
|
|
input wire wr_clk,
|
|
input wire [71:0] din,
|
|
input wire wr_en,
|
|
output wire full,
|
|
output wire [9:0] wr_data_count,
|
|
input wire rd_clk,
|
|
output wire [71:0] dout,
|
|
input wire rd_en,
|
|
output wire empty,
|
|
output wire [9:0] rd_data_count
|
|
);
|
|
|
|
fifo_2clk_xpm_core #(
|
|
.FIFO_DEPTH (512),
|
|
.COUNT_WIDTH (10),
|
|
.CDC_SYNC_STAGES (2),
|
|
.MEMORY_TYPE ("block")
|
|
) impl_i (
|
|
.rst (rst),
|
|
.wr_clk (wr_clk),
|
|
.din (din),
|
|
.wr_en (wr_en),
|
|
.full (full),
|
|
.wr_data_count(wr_data_count),
|
|
.rd_clk (rd_clk),
|
|
.dout (dout),
|
|
.rd_en (rd_en),
|
|
.empty (empty),
|
|
.rd_data_count(rd_data_count)
|
|
);
|
|
|
|
endmodule
|
|
|
|
`default_nettype wire
|