61782b02d7
Co-authored-by: Andrew Moch <Andrew.Moch@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com> Co-authored-by: Joerg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Kumaran Subramoniam <kumaran.subramoniam@ni.com> Co-authored-by: Max Köhler <max.koehler@ni.com> Co-authored-by: Michael Auchter <michael.auchter@ni.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Co-authored-by: Hector Rubio <hrubio@ni.com> Original-commit: 6d3765605262016a80f71e36357f749ea35cbe5a
455 lines
21 KiB
Verilog
455 lines
21 KiB
Verilog
//
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// Copyright 2021 Ettus Research, A National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0
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//
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// Module: x4xx_core
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//
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// Description:
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//
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// This module contains the core infrastructure for RFNoC, such as the
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// motherboard register, timekeeper, and RFNoC image core.
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//
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// Parameters:
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//
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// NUM_DBOARDS : Number of daughter boards
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// REG_DWIDTH : Width of the AXI4-Lite data bus (must be 32 or 64)
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// REG_AWIDTH : Width of the address bus
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// CHDR_CLK_RATE : rfnoc_chdr_clk rate in Hz
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// NUM_CHANNELS : Total number of channels
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// CHDR_W : CHDR width used by RFNoC
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// MTU : Log2 of maximum transmission unit in CHDR_W sized words
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// RFNOC_PROTOVER : RFNoC protocol version (major[7:0], minor[7:0])
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// RADIO_SPC : Number of samples per radio clock cycle
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//
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module x4xx_core #(
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parameter NUM_DBOARDS = 2,
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parameter REG_DWIDTH = 32,
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parameter REG_AWIDTH = 32,
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parameter CHDR_CLK_RATE = 200000000,
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parameter NUM_CHANNELS = 4,
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parameter CHDR_W = 64,
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parameter MTU = $clog2(8192 / (CHDR_W/8)),
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parameter RFNOC_PROTOVER = {8'd1, 8'd0},
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parameter RADIO_SPC = 1
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) (
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// Clocks and resets
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input radio_clk,
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input radio_rst,
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input radio_clk_2x,
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input rfnoc_chdr_clk,
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input rfnoc_chdr_rst,
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input rfnoc_ctrl_clk,
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input rfnoc_ctrl_rst,
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// AXI-Lite interface (for motherboard registers)
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input s_axi_aclk,
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input s_axi_aresetn,
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input [ REG_AWIDTH-1:0] s_axi_awaddr,
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input s_axi_awvalid,
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output s_axi_awready,
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input [ REG_DWIDTH-1:0] s_axi_wdata,
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input [REG_DWIDTH/8-1:0] s_axi_wstrb,
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input s_axi_wvalid,
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output s_axi_wready,
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output [ 1:0] s_axi_bresp,
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output s_axi_bvalid,
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input s_axi_bready,
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input [ REG_AWIDTH-1:0] s_axi_araddr,
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input s_axi_arvalid,
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output s_axi_arready,
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output [ REG_DWIDTH-1:0] s_axi_rdata,
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output [ 1:0] s_axi_rresp,
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output s_axi_rvalid,
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input s_axi_rready,
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// PPS and Clock Control
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input pps_radioclk,
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output [ 1:0] pps_select,
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output [ 1:0] trig_io_select,
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output pll_sync_trigger,
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output [ 7:0] pll_sync_delay,
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input pll_sync_done,
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output [ 7:0] pps_brc_delay,
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output [25:0] pps_prc_delay,
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output [ 1:0] prc_rc_divider,
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output pps_rc_enabled,
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// Radio Data
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input [32*RADIO_SPC*NUM_CHANNELS-1:0] rx_data,
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input [ NUM_CHANNELS-1:0] rx_stb,
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output [ NUM_CHANNELS-1:0] rx_running,
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//
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output [32*RADIO_SPC*NUM_CHANNELS-1:0] tx_data,
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input [ NUM_CHANNELS-1:0] tx_stb,
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output [ NUM_CHANNELS-1:0] tx_running,
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// DMA
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output [CHDR_W-1:0] dmao_tdata,
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output dmao_tlast,
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output dmao_tvalid,
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input dmao_tready,
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input [CHDR_W-1:0] dmai_tdata,
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input dmai_tlast,
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input dmai_tvalid,
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output dmai_tready,
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// e2v (Ethernet to CHDR)
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output [CHDR_W*8-1:0] v2e_tdata,
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output [ 8-1:0] v2e_tvalid,
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output [ 8-1:0] v2e_tlast,
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input [ 8-1:0] v2e_tready,
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// v2e (CHDR to Ethernet)
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input [CHDR_W*8-1:0] e2v_tdata,
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input [ 8-1:0] e2v_tlast,
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input [ 8-1:0] e2v_tvalid,
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output [ 8-1:0] e2v_tready,
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// GPIO to DIO board (Domain: rfnoc_ctrl_clk)
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output wire [11:0] gpio_en_a,
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output wire [11:0] gpio_en_b,
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// GPIO to DIO board (async)
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input wire [11:0] gpio_in_a,
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input wire [11:0] gpio_in_b,
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output wire [11:0] gpio_out_a,
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output wire [11:0] gpio_out_b,
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// Misc
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input [31:0] qsfp_port_0_0_info,
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input [31:0] qsfp_port_0_1_info,
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input [31:0] qsfp_port_0_2_info,
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input [31:0] qsfp_port_0_3_info,
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input [31:0] qsfp_port_1_0_info,
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input [31:0] qsfp_port_1_1_info,
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input [31:0] qsfp_port_1_2_info,
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input [31:0] qsfp_port_1_3_info,
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output [15:0] device_id,
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output mfg_test_en_fabric_clk,
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output mfg_test_en_gty_rcv_clk,
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input fpga_aux_ref,
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// Radio Control Ports
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output wire [63:0] radio_time,
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output wire radio_time_stb,
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output wire [ 1*NUM_DBOARDS-1:0] m_ctrlport_radio_req_wr,
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output wire [ 1*NUM_DBOARDS-1:0] m_ctrlport_radio_req_rd,
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output wire [ 20*NUM_DBOARDS-1:0] m_ctrlport_radio_req_addr,
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output wire [ 32*NUM_DBOARDS-1:0] m_ctrlport_radio_req_data,
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output wire [ 4*NUM_DBOARDS-1:0] m_ctrlport_radio_req_byte_en,
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output wire [ 1*NUM_DBOARDS-1:0] m_ctrlport_radio_req_has_time,
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output wire [ 64*NUM_DBOARDS-1:0] m_ctrlport_radio_req_time,
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input wire [ 1*NUM_DBOARDS-1:0] m_ctrlport_radio_resp_ack,
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input wire [ 2*NUM_DBOARDS-1:0] m_ctrlport_radio_resp_status,
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input wire [ 32*NUM_DBOARDS-1:0] m_ctrlport_radio_resp_data,
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// RF Reset Control
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output wire start_nco_reset,
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input wire nco_reset_done,
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output wire adc_reset_pulse,
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output wire dac_reset_pulse,
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// Version (Constant)
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// Each component consists of a 96-bit vector (refer to versioning_utils.vh)
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input wire [64*96-1:0] version_info
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);
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//---------------------------------------------------------------------------
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// AXI-Lite to CtrlPort Bridge
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//---------------------------------------------------------------------------
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wire [19:0] ctrlport_req_addr;
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wire [ 3:0] ctrlport_req_byte_en;
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wire [31:0] ctrlport_req_data;
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wire ctrlport_req_has_time;
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wire [ 9:0] ctrlport_req_portid;
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wire ctrlport_req_rd;
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wire [15:0] ctrlport_req_rem_epid;
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wire [ 9:0] ctrlport_req_rem_portid;
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wire [63:0] ctrlport_req_time;
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wire ctrlport_req_wr;
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wire ctrlport_resp_ack;
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wire [31:0] ctrlport_resp_data;
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wire [ 1:0] ctrlport_resp_status;
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`include "../../lib/rfnoc/core/ctrlport.vh"
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axil_ctrlport_master
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# (
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.TIMEOUT (10), //integer:=10
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.AXI_AWIDTH (REG_AWIDTH), //integer:=17
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.CTRLPORT_AWIDTH (CTRLPORT_ADDR_W)) //integer:=17
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axil_ctrlport_masterx (
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.s_axi_aclk (s_axi_aclk), //in wire
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.s_axi_aresetn (s_axi_aresetn), //in wire
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.s_axi_awaddr (s_axi_awaddr), //in wire[(AXI_AWIDTH-1):0]
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.s_axi_awvalid (s_axi_awvalid), //in wire
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.s_axi_awready (s_axi_awready), //out wire
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.s_axi_wdata (s_axi_wdata), //in wire[31:0]
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.s_axi_wstrb (s_axi_wstrb), //in wire[3:0]
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.s_axi_wvalid (s_axi_wvalid), //in wire
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.s_axi_wready (s_axi_wready), //out wire
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.s_axi_bresp (s_axi_bresp), //out wire[1:0]
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.s_axi_bvalid (s_axi_bvalid), //out wire
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.s_axi_bready (s_axi_bready), //in wire
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.s_axi_araddr (s_axi_araddr), //in wire[(AXI_AWIDTH-1):0]
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.s_axi_arvalid (s_axi_arvalid), //in wire
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.s_axi_arready (s_axi_arready), //out wire
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.s_axi_rdata (s_axi_rdata), //out wire[31:0]
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.s_axi_rresp (s_axi_rresp), //out wire[1:0]
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.s_axi_rvalid (s_axi_rvalid), //out wire
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.s_axi_rready (s_axi_rready), //in wire
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.m_ctrlport_req_wr (ctrlport_req_wr), //out wire
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.m_ctrlport_req_rd (ctrlport_req_rd), //out wire
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.m_ctrlport_req_addr (ctrlport_req_addr), //out wire[19:0]
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.m_ctrlport_req_portid (ctrlport_req_portid), //out wire[9:0]
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.m_ctrlport_req_rem_epid (ctrlport_req_rem_epid), //out wire[15:0]
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.m_ctrlport_req_rem_portid (ctrlport_req_rem_portid), //out wire[9:0]
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.m_ctrlport_req_data (ctrlport_req_data), //out wire[31:0]
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.m_ctrlport_req_byte_en (ctrlport_req_byte_en), //out wire[3:0]
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.m_ctrlport_req_has_time (ctrlport_req_has_time), //out wire
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.m_ctrlport_req_time (ctrlport_req_time), //out wire[63:0]
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.m_ctrlport_resp_ack (ctrlport_resp_ack), //in wire
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.m_ctrlport_resp_status (ctrlport_resp_status), //in wire[1:0]
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.m_ctrlport_resp_data (ctrlport_resp_data)); //in wire[31:0]
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//---------------------------------------------------------------------------
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// Common Components
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//---------------------------------------------------------------------------
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wire ctrlport_rst;
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reset_sync reset_sync_ctrlport (
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.clk (s_axi_aclk),
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.reset_in (~s_axi_aresetn),
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.reset_out (ctrlport_rst)
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);
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x4xx_core_common #(
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.CHDR_CLK_RATE (CHDR_CLK_RATE),
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.CHDR_W (CHDR_W),
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.RFNOC_PROTOVER (RFNOC_PROTOVER),
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.PCIE_PRESENT (0)
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) x4xx_core_common_i (
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.radio_clk (radio_clk),
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.radio_rst (radio_rst),
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.rfnoc_chdr_clk (rfnoc_chdr_clk),
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.rfnoc_chdr_rst (rfnoc_chdr_rst),
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.rfnoc_ctrl_clk (rfnoc_ctrl_clk),
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.rfnoc_ctrl_rst (rfnoc_ctrl_rst),
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.ctrlport_clk (s_axi_aclk),
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.ctrlport_rst (ctrlport_rst),
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.s_ctrlport_req_wr (ctrlport_req_wr),
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.s_ctrlport_req_rd (ctrlport_req_rd),
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.s_ctrlport_req_addr (ctrlport_req_addr),
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.s_ctrlport_req_portid (ctrlport_req_portid),
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.s_ctrlport_req_rem_epid (ctrlport_req_rem_epid),
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.s_ctrlport_req_rem_portid (ctrlport_req_rem_portid),
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.s_ctrlport_req_data (ctrlport_req_data),
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.s_ctrlport_req_byte_en (ctrlport_req_byte_en),
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.s_ctrlport_req_has_time (ctrlport_req_has_time),
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.s_ctrlport_req_time (ctrlport_req_time),
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.s_ctrlport_resp_ack (ctrlport_resp_ack),
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.s_ctrlport_resp_status (ctrlport_resp_status),
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.s_ctrlport_resp_data (ctrlport_resp_data),
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.pps_radioclk (pps_radioclk),
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.pps_select (pps_select),
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.trig_io_select (trig_io_select),
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.pll_sync_trigger (pll_sync_trigger),
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.pll_sync_delay (pll_sync_delay),
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.pll_sync_done (pll_sync_done),
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.pps_brc_delay (pps_brc_delay),
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.pps_prc_delay (pps_prc_delay),
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.prc_rc_divider (prc_rc_divider),
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.pps_rc_enabled (pps_rc_enabled),
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.radio_spc (RADIO_SPC),
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.radio_time (radio_time),
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.sample_rx_stb (radio_time_stb),
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.gpio_in_a (gpio_in_a),
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.gpio_in_b (gpio_in_b),
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.gpio_out_a (gpio_out_a),
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.gpio_out_b (gpio_out_b),
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.gpio_en_a (gpio_en_a),
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.gpio_en_b (gpio_en_b),
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.gpio_in_fabric_a (),
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.gpio_in_fabric_b (),
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.gpio_out_fabric_a (12'b0),
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.gpio_out_fabric_b (12'b0),
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.qsfp_port_0_0_info (qsfp_port_0_0_info),
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.qsfp_port_0_1_info (qsfp_port_0_1_info),
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.qsfp_port_0_2_info (qsfp_port_0_2_info),
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.qsfp_port_0_3_info (qsfp_port_0_3_info),
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.qsfp_port_1_0_info (qsfp_port_1_0_info),
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.qsfp_port_1_1_info (qsfp_port_1_1_info),
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.qsfp_port_1_2_info (qsfp_port_1_2_info),
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.qsfp_port_1_3_info (qsfp_port_1_3_info),
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.device_id (device_id),
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.mfg_test_en_fabric_clk (mfg_test_en_fabric_clk),
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.mfg_test_en_gty_rcv_clk (mfg_test_en_gty_rcv_clk),
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.fpga_aux_ref (fpga_aux_ref),
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.version_info (version_info)
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);
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// Provide information for ctrlport timed commands
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assign radio_time_stb = rx_stb[0];
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//---------------------------------------------------------------------------
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// RFNoC Image Core
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//---------------------------------------------------------------------------
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// Calculate how may bits wide each channel is
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localparam CHAN_W = 32 * RADIO_SPC;
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wire [ 1*NUM_DBOARDS-1:0] ctrlport_radio_req_wr;
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wire [ 1*NUM_DBOARDS-1:0] ctrlport_radio_req_rd;
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wire [ 20*NUM_DBOARDS-1:0] ctrlport_radio_req_addr;
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wire [ 32*NUM_DBOARDS-1:0] ctrlport_radio_req_data;
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wire [ 4*NUM_DBOARDS-1:0] ctrlport_radio_req_byte_en;
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wire [ 1*NUM_DBOARDS-1:0] ctrlport_radio_req_has_time;
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wire [ 64*NUM_DBOARDS-1:0] ctrlport_radio_req_time;
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wire [ 1*NUM_DBOARDS-1:0] ctrlport_radio_resp_ack;
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wire [ 2*NUM_DBOARDS-1:0] ctrlport_radio_resp_status;
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wire [ 32*NUM_DBOARDS-1:0] ctrlport_radio_resp_data;
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rfnoc_image_core #(
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.CHDR_W (CHDR_W),
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.MTU (MTU),
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.PROTOVER (RFNOC_PROTOVER),
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.RADIO_NIPC (RADIO_SPC)
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) rfnoc_image_core_i (
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.chdr_aclk (rfnoc_chdr_clk),
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.ctrl_aclk (rfnoc_ctrl_clk),
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.core_arst (rfnoc_ctrl_rst),
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.radio_clk (radio_clk),
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.radio_2x_clk (radio_clk_2x),
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.device_id (device_id),
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.m_ctrlport_radio0_req_wr (ctrlport_radio_req_wr [0* 1+: 1]),
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.m_ctrlport_radio0_req_rd (ctrlport_radio_req_rd [0* 1+: 1]),
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.m_ctrlport_radio0_req_addr (ctrlport_radio_req_addr [0*20+:20]),
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.m_ctrlport_radio0_req_data (ctrlport_radio_req_data [0*32+:32]),
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.m_ctrlport_radio0_req_byte_en (ctrlport_radio_req_byte_en [0* 4+: 4]),
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.m_ctrlport_radio0_req_has_time (ctrlport_radio_req_has_time[0* 1+: 1]),
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.m_ctrlport_radio0_req_time (ctrlport_radio_req_time [0*64+:64]),
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.m_ctrlport_radio0_resp_ack (ctrlport_radio_resp_ack [0* 1+: 1]),
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.m_ctrlport_radio0_resp_status (ctrlport_radio_resp_status [0* 2+: 2]),
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.m_ctrlport_radio0_resp_data (ctrlport_radio_resp_data [0*32+:32]),
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.m_ctrlport_radio1_req_wr (ctrlport_radio_req_wr [1* 1+: 1]),
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.m_ctrlport_radio1_req_rd (ctrlport_radio_req_rd [1* 1+: 1]),
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.m_ctrlport_radio1_req_addr (ctrlport_radio_req_addr [1*20+:20]),
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.m_ctrlport_radio1_req_data (ctrlport_radio_req_data [1*32+:32]),
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.m_ctrlport_radio1_req_byte_en (ctrlport_radio_req_byte_en [1* 4+: 4]),
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.m_ctrlport_radio1_req_has_time (ctrlport_radio_req_has_time[1* 1+: 1]),
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.m_ctrlport_radio1_req_time (ctrlport_radio_req_time [1*64+:64]),
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.m_ctrlport_radio1_resp_ack (ctrlport_radio_resp_ack [1* 1+: 1]),
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.m_ctrlport_radio1_resp_status (ctrlport_radio_resp_status [1* 2+: 2]),
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.m_ctrlport_radio1_resp_data (ctrlport_radio_resp_data [1*32+:32]),
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.radio_rx_stb_radio1 ({ rx_stb[3], rx_stb[2] }),
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.radio_rx_data_radio1 ({ rx_data[3*CHAN_W+:CHAN_W], rx_data[2*CHAN_W+:CHAN_W]}),
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.radio_rx_running_radio1 ({rx_running[3], rx_running[2] }),
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.radio_tx_stb_radio1 ({ tx_stb[3], tx_stb[2] }),
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.radio_tx_data_radio1 ({ tx_data[3*CHAN_W+:CHAN_W], tx_data[2*CHAN_W+:CHAN_W]}),
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.radio_tx_running_radio1 ({tx_running[3], tx_running[2] }),
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|
.radio_rx_stb_radio0 ({ rx_stb[1], rx_stb[0] }),
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|
.radio_rx_data_radio0 ({ rx_data[1*CHAN_W+:CHAN_W], rx_data[0*CHAN_W+:CHAN_W]}),
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|
.radio_rx_running_radio0 ({rx_running[1], rx_running[0] }),
|
|
.radio_tx_stb_radio0 ({ tx_stb[1], tx_stb[0] }),
|
|
.radio_tx_data_radio0 ({ tx_data[1*CHAN_W+:CHAN_W], tx_data[0*CHAN_W+:CHAN_W]}),
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|
.radio_tx_running_radio0 ({tx_running[1], tx_running[0] }),
|
|
.radio_time (radio_time),
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|
.s_eth0_tdata (e2v_tdata [0*CHDR_W +: CHDR_W]),
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|
.s_eth0_tlast (e2v_tlast [0* 1 +: 1]),
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|
.s_eth0_tvalid (e2v_tvalid [0* 1 +: 1]),
|
|
.s_eth0_tready (e2v_tready [0* 1 +: 1]),
|
|
.m_eth0_tdata (v2e_tdata [0*CHDR_W +: CHDR_W]),
|
|
.m_eth0_tlast (v2e_tlast [0* 1 +: 1]),
|
|
.m_eth0_tvalid (v2e_tvalid [0* 1 +: 1]),
|
|
.m_eth0_tready (v2e_tready [0* 1 +: 1]),
|
|
.s_eth1_tdata (e2v_tdata [1*CHDR_W +: CHDR_W]),
|
|
.s_eth1_tlast (e2v_tlast [1* 1 +: 1]),
|
|
.s_eth1_tvalid (e2v_tvalid [1* 1 +: 1]),
|
|
.s_eth1_tready (e2v_tready [1* 1 +: 1]),
|
|
.m_eth1_tdata (v2e_tdata [1*CHDR_W +: CHDR_W]),
|
|
.m_eth1_tlast (v2e_tlast [1* 1 +: 1]),
|
|
.m_eth1_tvalid (v2e_tvalid [1* 1 +: 1]),
|
|
.m_eth1_tready (v2e_tready [1* 1 +: 1]),
|
|
.s_eth2_tdata (e2v_tdata [2*CHDR_W +: CHDR_W]),
|
|
.s_eth2_tlast (e2v_tlast [2* 1 +: 1]),
|
|
.s_eth2_tvalid (e2v_tvalid [2* 1 +: 1]),
|
|
.s_eth2_tready (e2v_tready [2* 1 +: 1]),
|
|
.m_eth2_tdata (v2e_tdata [2*CHDR_W +: CHDR_W]),
|
|
.m_eth2_tlast (v2e_tlast [2* 1 +: 1]),
|
|
.m_eth2_tvalid (v2e_tvalid [2* 1 +: 1]),
|
|
.m_eth2_tready (v2e_tready [2* 1 +: 1]),
|
|
.s_eth3_tdata (e2v_tdata [3*CHDR_W +: CHDR_W]),
|
|
.s_eth3_tlast (e2v_tlast [3* 1 +: 1]),
|
|
.s_eth3_tvalid (e2v_tvalid [3* 1 +: 1]),
|
|
.s_eth3_tready (e2v_tready [3* 1 +: 1]),
|
|
.m_eth3_tdata (v2e_tdata [3*CHDR_W +: CHDR_W]),
|
|
.m_eth3_tlast (v2e_tlast [3* 1 +: 1]),
|
|
.m_eth3_tvalid (v2e_tvalid [3* 1 +: 1]),
|
|
.m_eth3_tready (v2e_tready [3* 1 +: 1]),
|
|
.s_eth4_tdata (e2v_tdata [4*CHDR_W +: CHDR_W]),
|
|
.s_eth4_tlast (e2v_tlast [4* 1 +: 1]),
|
|
.s_eth4_tvalid (e2v_tvalid [4* 1 +: 1]),
|
|
.s_eth4_tready (e2v_tready [4* 1 +: 1]),
|
|
.m_eth4_tdata (v2e_tdata [4*CHDR_W +: CHDR_W]),
|
|
.m_eth4_tlast (v2e_tlast [4* 1 +: 1]),
|
|
.m_eth4_tvalid (v2e_tvalid [4* 1 +: 1]),
|
|
.m_eth4_tready (v2e_tready [4* 1 +: 1]),
|
|
.s_dma_tdata (dmai_tdata),
|
|
.s_dma_tlast (dmai_tlast),
|
|
.s_dma_tvalid (dmai_tvalid),
|
|
.s_dma_tready (dmai_tready),
|
|
.m_dma_tdata (dmao_tdata),
|
|
.m_dma_tlast (dmao_tlast),
|
|
.m_dma_tvalid (dmao_tvalid),
|
|
.m_dma_tready (dmao_tready)
|
|
);
|
|
|
|
|
|
//-------------------------------------------------------------------------
|
|
// RF Timing Reset Control
|
|
//-------------------------------------------------------------------------
|
|
|
|
rfdc_timing_control #(
|
|
.NUM_DBOARDS (NUM_DBOARDS)
|
|
) rfdc_timing_control_i (
|
|
.clk (radio_clk),
|
|
.rst (radio_rst),
|
|
.time_now (radio_time),
|
|
.time_now_stb (radio_time_stb),
|
|
.time_ignore_bits ($clog2(RADIO_SPC)),
|
|
.s_ctrlport_req_wr (ctrlport_radio_req_wr),
|
|
.s_ctrlport_req_rd (ctrlport_radio_req_rd),
|
|
.s_ctrlport_req_addr (ctrlport_radio_req_addr),
|
|
.s_ctrlport_req_data (ctrlport_radio_req_data),
|
|
.s_ctrlport_req_byte_en (ctrlport_radio_req_byte_en),
|
|
.s_ctrlport_req_has_time (ctrlport_radio_req_has_time),
|
|
.s_ctrlport_req_time (ctrlport_radio_req_time),
|
|
.s_ctrlport_resp_ack (ctrlport_radio_resp_ack),
|
|
.s_ctrlport_resp_status (ctrlport_radio_resp_status),
|
|
.s_ctrlport_resp_data (ctrlport_radio_resp_data),
|
|
.m_ctrlport_req_wr (m_ctrlport_radio_req_wr),
|
|
.m_ctrlport_req_rd (m_ctrlport_radio_req_rd),
|
|
.m_ctrlport_req_addr (m_ctrlport_radio_req_addr),
|
|
.m_ctrlport_req_data (m_ctrlport_radio_req_data),
|
|
.m_ctrlport_req_byte_en (m_ctrlport_radio_req_byte_en),
|
|
.m_ctrlport_req_has_time (m_ctrlport_radio_req_has_time),
|
|
.m_ctrlport_req_time (m_ctrlport_radio_req_time),
|
|
.m_ctrlport_resp_ack (m_ctrlport_radio_resp_ack),
|
|
.m_ctrlport_resp_status (m_ctrlport_radio_resp_status),
|
|
.m_ctrlport_resp_data (m_ctrlport_radio_resp_data),
|
|
.start_nco_reset (start_nco_reset),
|
|
.nco_reset_done (nco_reset_done),
|
|
.adc_reset_pulse (adc_reset_pulse),
|
|
.dac_reset_pulse (dac_reset_pulse)
|
|
);
|
|
|
|
endmodule
|