Files
b210-k7-fpga/sim/rfnoc/test/ChdrIfaceBfm/Makefile
T
Wade Fife 2711d7f618 sim: Add ChdrIfaceBfm test
Original-commit: 6f42ab7c1c962bfc425b6790fe41b2c14769e561
2020-03-09 13:43:05 -05:00

33 lines
1.0 KiB
Makefile

#
# Copyright 2020 Ettus Research, A National Instruments Company
#
# SPDX-License-Identifier: LGPL-3.0-or-later
#
#-------------------------------------------------
# Top-of-Makefile
#-------------------------------------------------
# Define BASE_DIR to point to the "top" dir
BASE_DIR = $(abspath ../../../../top)
# Include viv_sim_preamble after defining BASE_DIR
include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
#-------------------------------------------------
# Testbench Specific
#-------------------------------------------------
# Define only one toplevel module
SIM_TOP = ChdrIfaceBfm_tb
# Add test bench, user design under test, and
# additional user created files
SIM_SRCS = \
$(abspath ChdrIfaceBfm_tb.sv)
#-------------------------------------------------
# Bottom-of-Makefile
#-------------------------------------------------
# Include all simulator specific makefiles here
# Each should define a unique target to simulate
# e.g. xsim, vsim, etc and a common "clean" target
include $(BASE_DIR)/../tools/make/viv_simulator.mak