44 lines
1.1 KiB
Verilog
44 lines
1.1 KiB
Verilog
//
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// Copyright 2011-2012 Ettus Research LLC
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// Copyright 2018 Ettus Research, a National Instruments Company
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// Copyright 2022 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: setting_reg
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//
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// Description:
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//
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// A settings register is a peripheral for the settings register bus. When
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// the settings register sees the strobe and a matching address, the outputs
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// will be become registered to the given input bus.
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//
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module setting_reg #(
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parameter my_addr = 0,
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parameter awidth = 8,
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parameter width = 32,
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parameter at_reset = 0
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) (
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input wire clk,
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input wire rst,
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input wire strobe,
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input wire [awidth-1:0] addr,
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input wire [ 31:0] in,
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output reg [ width-1:0] out,
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output reg changed
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);
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always @(posedge clk)
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if(rst) begin
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out <= at_reset;
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changed <= 1'b0;
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end else begin
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if(strobe && (my_addr == addr)) begin
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out <= in[width-1:0];
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changed <= 1'b1;
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end else begin
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changed <= 1'b0;
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end
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end
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endmodule // setting_reg
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