42 lines
1.6 KiB
Systemverilog
42 lines
1.6 KiB
Systemverilog
//
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// Copyright 2022 Ettus Research, A National Instruments Company
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: pl_cpld_regmap_utils.vh
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// Description:
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// The constants in this file are autogenerated by XmlParse.
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//===============================================================================
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// A numerically ordered list of registers and their HDL source files
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//===============================================================================
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// BASE : 0x0 (cpld_interface.v)
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// MB_CPLD : 0x8000 (cpld_interface.v)
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// DB0_CPLD : 0x10000 (cpld_interface.v)
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// DB1_CPLD : 0x18000 (cpld_interface.v)
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//===============================================================================
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// RegTypes
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//===============================================================================
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//===============================================================================
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// Register Group PL_CPLD_WINDOWS
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//===============================================================================
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// BASE Window (from cpld_interface.v)
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localparam BASE = 'h0; // Window Offset
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localparam BASE_SIZE = 'h40; // size in bytes
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// MB_CPLD Window (from cpld_interface.v)
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localparam MB_CPLD = 'h8000; // Window Offset
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localparam MB_CPLD_SIZE = 'h8000; // size in bytes
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// DB0_CPLD Window (from cpld_interface.v)
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localparam DB0_CPLD = 'h10000; // Window Offset
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localparam DB0_CPLD_SIZE = 'h8000; // size in bytes
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// DB1_CPLD Window (from cpld_interface.v)
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localparam DB1_CPLD = 'h18000; // Window Offset
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localparam DB1_CPLD_SIZE = 'h8000; // size in bytes
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