Javier Valenzuela
a6fc53b4e6
The main changes included are: - Variant-dependent pin-out instantiation. - Update clocking scheme in top level file to include XO3 PLL - Add ability to shift outgoing data for the GPIO communication interface with the X410 FPGA. - Include project files required to build the XO3 variant of the ZBX CPLD. - Add build flow for Lattice Diamond designs. - Add ability to build XO3 variant of ZBX CPLD. Original-commit: 2c7813acb21383f302353a1b6cf57f0946fa0b6b
220 lines
7.1 KiB
Verilog
220 lines
7.1 KiB
Verilog
//
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// Copyright 2021 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: ctrlport_byte_deserializer
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//
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// Description:
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// Slave interface of CtrlPort interface serialized as byte stream.
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// See description in ctrlport_byte_serializer module for more details.
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// Input and output data may be driven/registered using clocks with
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// different phases (but same frequency), this allows the capability
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// to facilitate meeting timing on this interface.
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//
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`default_nettype none
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module ctrlport_byte_deserializer (
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// clock domain used to register input data
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input wire ctrlport_clk,
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// clock domain used to drive output data
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input wire ctrlport_clk_adjusted,
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input wire ctrlport_rst,
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// Request
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output wire m_ctrlport_req_wr,
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output wire m_ctrlport_req_rd,
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output wire [19:0] m_ctrlport_req_addr,
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output wire [31:0] m_ctrlport_req_data,
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// Response
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input wire m_ctrlport_resp_ack,
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input wire [ 1:0] m_ctrlport_resp_status,
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input wire [31:0] m_ctrlport_resp_data,
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// byte interface
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input wire [ 7:0] bytestream_data_in,
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input wire bytestream_valid_in,
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input wire bytestream_direction,
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output reg [ 7:0] bytestream_data_out = 8'b0,
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output reg bytestream_valid_out = 1'b0,
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output reg bytestream_output_enable = 1'b0
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);
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`include "../../../lib/rfnoc/core/ctrlport.vh"
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//---------------------------------------------------------------
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// transfer constants
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//---------------------------------------------------------------
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// derived from transaction specification
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localparam NUM_BYTES_RX_READ = 2;
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localparam NUM_BYTES_TX_READ = 5;
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localparam NUM_BYTES_RX_WRITE = 6;
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localparam NUM_BYTES_TX_WRITE = 1;
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localparam SPI_TRANSFER_ADDRESS_WIDTH = 15;
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//----------------------------------------------------------
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// handle transfer
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//----------------------------------------------------------
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localparam INIT_RX = 2'd0;
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localparam RECEIVE = 2'd1;
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localparam WAIT_RESPONSE = 2'd2;
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localparam SENDING = 2'd3;
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// internal registers
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reg [ 1:0] state = INIT_RX;
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reg [NUM_BYTES_RX_WRITE*8-1:0] request_cache = {NUM_BYTES_RX_WRITE*8 {1'b0}};
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reg [ NUM_BYTES_TX_READ*8-1:0] response_cache = {NUM_BYTES_TX_READ*8 {1'b0}};
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reg [ 2:0] request_byte_counter = 3'b0;
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reg [ 2:0] response_byte_counter = 3'b0;
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reg transfer_complete = 1'b0;
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reg write_transfer = 1'b0;
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// input registers to relax input timing
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reg [7:0] bytestream_data_in_reg = 8'b0;
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reg bytestream_valid_in_reg = 1'b0;
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reg bytestream_direction_reg = 1'b0;
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always @ (posedge ctrlport_clk) begin
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bytestream_data_in_reg <= bytestream_data_in;
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bytestream_valid_in_reg <= bytestream_valid_in;
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bytestream_direction_reg <= bytestream_direction;
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end
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// state machine
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always @ (posedge ctrlport_clk) begin
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if (ctrlport_rst) begin
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state <= INIT_RX;
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request_byte_counter <= 3'b0;
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transfer_complete <= 1'b0;
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response_byte_counter <= 3'b0;
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end else begin
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// default assignments
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transfer_complete <= 1'b0;
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case (state)
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// additional cycle for switching to make sure valid signal is driven
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// from master when being in RECEIVE state
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INIT_RX: begin
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request_byte_counter <= 3'b0;
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if (bytestream_direction_reg == 0) begin
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state <= RECEIVE;
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end
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end
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// wait for reception of request from master
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RECEIVE: begin
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if (bytestream_valid_in_reg) begin
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request_byte_counter <= request_byte_counter + 1'b1;
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request_cache <= {request_cache[NUM_BYTES_RX_WRITE*8-9:0], bytestream_data_in_reg};
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// capture write or read
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if (request_byte_counter == 0) begin
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write_transfer <= bytestream_data_in_reg[7];
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end
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// wait until request completes
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if ((write_transfer && request_byte_counter == NUM_BYTES_RX_WRITE-1) ||
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(~write_transfer && request_byte_counter == NUM_BYTES_RX_READ-1)) begin
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transfer_complete <= 1'b1;
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state <= WAIT_RESPONSE;
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end
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end
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// Workaround for missing pull down resistor:
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// Use pull up and schmitt trigger to detect FPGA reload by line going high unexpectedly
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if (bytestream_direction_reg == 1) begin
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state <= INIT_RX;
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end
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end
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WAIT_RESPONSE: begin
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request_byte_counter <= 3'b0;
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response_byte_counter <= 3'b0;
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if (m_ctrlport_resp_ack) begin
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state <= SENDING;
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end
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//abort by host
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if (bytestream_direction_reg == 0) begin
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state <= INIT_RX;
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end
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end
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SENDING: begin
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response_byte_counter <= response_byte_counter + 1'b1;
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// wait until request completes
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if ((write_transfer && response_byte_counter == NUM_BYTES_TX_WRITE-1) ||
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(~write_transfer && response_byte_counter == NUM_BYTES_TX_READ-1)) begin
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state <= INIT_RX;
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end
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//abort by host
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if (bytestream_direction_reg == 0) begin
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state <= INIT_RX;
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end
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end
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default: begin
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state <= INIT_RX;
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end
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endcase
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end
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end
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// Output data control
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always @ (posedge ctrlport_clk_adjusted) begin
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if (ctrlport_rst) begin
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bytestream_valid_out <= 1'b0;
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bytestream_output_enable <= 1'b0;
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end else begin
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bytestream_valid_out <= 1'b0;
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// direction defined by master
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bytestream_output_enable <= bytestream_direction;
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case (state)
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WAIT_RESPONSE: begin
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if (write_transfer) begin
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response_cache <= {5'b0, 1'b1, m_ctrlport_resp_status, 32'b0};
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end else begin
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response_cache <= {m_ctrlport_resp_data, 5'b0, 1'b1, m_ctrlport_resp_status};
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end
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end
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SENDING: begin
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bytestream_valid_out <= 1'b1;
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bytestream_data_out <= response_cache[NUM_BYTES_TX_READ*8-8+:8];
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response_cache <= {response_cache[NUM_BYTES_TX_READ*8-9:0], 8'b0};
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end
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default: begin
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// NOP
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end
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endcase
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end
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end
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//----------------------------------------------------------
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// assign request to ctrlport
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//----------------------------------------------------------
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assign m_ctrlport_req_wr = write_transfer & transfer_complete;
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assign m_ctrlport_req_rd = ~write_transfer & transfer_complete;
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assign m_ctrlport_req_data = request_cache[0+:CTRLPORT_DATA_W];
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assign m_ctrlport_req_addr = (write_transfer) ?
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// Skipping data in LSBs to get to the address for writes.
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{5'b0, request_cache[CTRLPORT_DATA_W+:SPI_TRANSFER_ADDRESS_WIDTH]} :
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// Full request = address of 2 bytes in LSBs.
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{5'b0, request_cache[0+:SPI_TRANSFER_ADDRESS_WIDTH]};
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endmodule
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`default_nettype wire
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