Andrew Moch 439c2af5e2 fpga: lib: Add xge features for new xport_sv ...

- Made some things optional to reduce logic when
   used with the new xport_sv:
   (1) Clocking to sys_clk
   (2) Preamble insertion
 - New options to CUTTHROUGH faster on the TX path.
   The new xport_sv already has a gate to accumulate at
   its clock crossing.


Original-commit: a68e7101167a4b5bf7b60ed90d963982aae735b8

2020-07-31 13:32:59 -05:00

..

axi64_to_xge64.v

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

axi_count_packets_in_fifo.v

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

Makefile.srcs

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

xge64_to_axi64.v

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

xge_handshake.v

Merge FPGA repository back into UHD repository

2020-01-28 09:35:36 -08:00

xge_mac_wrapper.v

fpga: lib: Add xge features for new xport_sv

2020-07-31 13:32:59 -05:00