Martin Braun
cf85a6d40c
Cores originate from https://github.com/secworks/sha256. Original-commit: c43c72db097cbb5ebe29b7fa81484cbeaf19516b
80 lines
2.4 KiB
Verilog
80 lines
2.4 KiB
Verilog
//======================================================================
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//
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// sha256_stream.v
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// --------
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// Top level wrapper for the SHA-256 hash function providing
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// a simple stream interface with 512 bit data access.
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//
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//
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// Author: Olof Kindgren
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// Copyright (c) 2016, Olof Kindgren
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or
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// without modification, are permitted provided that the following
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// conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//======================================================================
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`default_nettype wire
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module sha256_stream
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(input clk,
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input rst,
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input mode,
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input [511:0] s_tdata_i,
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input s_tlast_i,
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input s_tvalid_i,
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output s_tready_o,
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output [255:0] digest_o,
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output digest_valid_o);
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reg first_block;
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always @(posedge clk) begin
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if (s_tvalid_i & s_tready_o)
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first_block <= s_tlast_i;
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if (rst) begin
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first_block <= 1'b1;
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end
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end
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sha256_core core
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(.clk (clk),
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.reset_n (~rst),
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.init(s_tvalid_i & first_block),
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.next(s_tvalid_i & !first_block),
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.mode (mode),
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.block(s_tdata_i),
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.ready(s_tready_o),
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.digest (digest_o),
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.digest_valid (digest_valid_o));
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endmodule
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