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066948f87dbf0275f0dd53fd08300fa0da78df39
b210-k7-fpga/lib/control
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Wade Fife 066948f87d fpga: lib: Add ctrlport_to_regport bridge 
Original-commit: 5d9fb234d31fc5a13111c559a91a82e81c2487fc
2020-08-19 12:28:22 -05:00
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map
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
ad5662_auto_spi.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
arb_qualify_master.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_crossbar_intf.sv
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_crossbar_regport.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_crossbar.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_fifo_header.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_forwarding_cam.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_setting_reg.v
fpga: rfnoc: Add Signal Generator RFNoC block
2020-07-30 12:51:41 -05:00
axi_slave_mux.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
axi_test_vfifo.v
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2020-01-28 09:35:36 -08:00
axil_ctrlport_master.v
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2020-01-28 09:35:36 -08:00
axil_regport_master.v
fpga: lib: Fix writes in axil_regport_master
2020-06-04 11:53:10 -05:00
axil_to_ni_regport.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
bin2gray.v
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2020-01-28 09:35:36 -08:00
binary_encoder.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
ctrlport_to_regport.v
fpga: lib: Add ctrlport_to_regport bridge
2020-08-19 12:28:22 -05:00
db_control.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
fe_control.v
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2020-01-28 09:35:36 -08:00
filter_bad_sid.v
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2020-01-28 09:35:36 -08:00
gpio_atr_io.v
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2020-01-28 09:35:36 -08:00
gpio_atr.v
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2020-01-28 09:35:36 -08:00
gray2bin.v
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2020-01-28 09:35:36 -08:00
handshake.v
fpga: lib: add handshake to replace FIFO for ctrlport CDC
2020-08-13 07:46:14 -05:00
Makefile.srcs
fpga: lib: Add ctrlport_to_regport bridge
2020-08-19 12:28:22 -05:00
mdio_master.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
por_gen.v
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2020-01-28 09:35:36 -08:00
priority_encoder_one_hot.v
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2020-01-28 09:35:36 -08:00
priority_encoder.v
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2020-01-28 09:35:36 -08:00
pulse_stretch_min.v
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2020-01-28 09:35:36 -08:00
pulse_stretch.v
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pulse_synchronizer.v
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2020-01-28 09:35:36 -08:00
ram_2port_impl.vh
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ram_2port.v
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2020-01-28 09:35:36 -08:00
regport_resp_mux.v
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2020-01-28 09:35:36 -08:00
regport_to_settingsbus.v
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2020-01-28 09:35:36 -08:00
regport_to_xbar_settingsbus.v
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2020-01-28 09:35:36 -08:00
reset_sync.v
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2020-01-28 09:35:36 -08:00
s7_icap_wb.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
serial_to_settings_tb.v
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2020-01-28 09:35:36 -08:00
serial_to_settings.v
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setting_reg.v
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2020-01-28 09:35:36 -08:00
settings_bus_mux.v
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settings_bus_timed_2clk.v
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2020-01-28 09:35:36 -08:00
simple_i2c_core.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
simple_spi_core_64bit.v
fpga: lib: add extended spi core for 64bit
2020-06-17 07:13:20 -05:00
simple_spi_core.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
synchronizer_impl.v
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2020-01-28 09:35:36 -08:00
synchronizer.v
Merge FPGA repository back into UHD repository
2020-01-28 09:35:36 -08:00
user_settings.v
Merge FPGA repository back into UHD repository
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