Andrew Moch
05eb1bc2f1
The rnfoc/xport section is refactored in System Verilog to allow the
following improvements
(1) CPU_W - Sets the size of the c2e and e2c pipes. This can be run
at a different clock rate than the main ethernet pipe
(2) CHDR_W - Sets the size of the v2e and e2v pipes. This can be run
at a different clock rate than the main ethernet pipe
(3) ENET_W - Sets the size of the eth_tx and eth_rx pipes.
eth_interface_tb runs traffic from e2c,e2v,v2e,c2e simultaneously
against the original xport_sv implementation, and against the new
implementation with widths of 64/128/512. A chdr_management node
info request queries the port info of the node0 in the eth_interface.
eth_ifc_synth_test.sv can be compiled with the make xsim target to test
out the size of various configurations.
Original-commit: eed4988cc266a63370a4332351d02fadedde3a3b
82 lines
2.7 KiB
Makefile
82 lines
2.7 KiB
Makefile
#
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# Copyright 2020 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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#-------------------------------------------------
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# Top-of-Makefile
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#-------------------------------------------------
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# Define BASE_DIR to point to the "top" dir
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BASE_DIR = $(abspath ../../../../top)
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# Include viv_sim_preamble after defining BASE_DIR
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include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
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#-------------------------------------------------
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# Design Specific
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#-------------------------------------------------
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SYNTH_DUT = eth_ifc_synth_test
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# Include makefiles and sources for the DUT and its dependencies
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include $(BASE_DIR)/../lib/control/Makefile.srcs
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include $(BASE_DIR)/../lib/axi/Makefile.srcs
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include $(BASE_DIR)/../lib/axi4s_sv/Makefile.srcs
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include $(BASE_DIR)/../lib/packet_proc/Makefile.srcs
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include $(BASE_DIR)/../lib/xge_interface/Makefile.srcs
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include $(BASE_DIR)/../lib/fifo/Makefile.srcs
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include $(BASE_DIR)/../lib/rfnoc/utils/Makefile.srcs
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include $(BASE_DIR)/../lib/rfnoc/xport/Makefile.srcs
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include $(BASE_DIR)/../lib/rfnoc/xport_sv/Makefile.srcs
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include $(BASE_DIR)/../lib/rfnoc/crossbar/Makefile.srcs
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include $(BASE_DIR)/../lib/rfnoc/core/Makefile.srcs
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BUILD_IP_DIR = $(abspath $(BASE_DIR)/x300/build-ip/xc7k410tffg900-2)
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IP_SRC = \
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$(abspath $(BUILD_IP_DIR)/fifo_short_2clk/fifo_short_2clk_sim_netlist.v)
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# Xilinx IP wants lots of libraries
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MODELSIM_LIBS += secureip unimacro_ver unisims_ver xilinx_vip xpm
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MODELSIM_ARGS += glbl -t 1fs
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DESIGN_SRCS = $(abspath \
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eth_ifc_synth_test.sv \
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$(FIFO_SRCS) \
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$(CONTROL_LIB_SRCS) \
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$(AXI_SRCS) \
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$(AXI4S_SV_SRCS) \
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$(XGE_INTERFACE_SRCS) \
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$(PACKET_PROC_SRCS) \
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$(RFNOC_UTIL_SRCS) \
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$(RFNOC_XPORT_SRCS) \
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$(RFNOC_XPORT_SV_SRCS) \
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$(RFNOC_XBAR_SRCS) \
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$(RFNOC_CORE_SRCS) \
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$(IP_SRC) \
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)
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#-------------------------------------------------
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# Testbench Specific
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#-------------------------------------------------
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# Define only one toplevel module
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TB_TOP_MODULE ?= eth_ifc_all_tb
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#TB_TOP_MODULE ?= eth_ifc_synth_test
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SIM_TOP = $(TB_TOP_MODULE)
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SIM_SRCS = \
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$(abspath eth_ifc_tb.sv) \
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$(abspath $(TB_TOP_MODULE).sv)
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# supressing the following worthless reminder.
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#* Warning: M:/usrp4-hw/oss-repo/fpga/usrp3/lib/axi4s_sv/axi4s_remove_bytes.sv(228): (vlog-2583) [SVCHK] -
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# Extra checking for conflicts with always_comb and always_latch variables is done at vopt time
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SVLOG_ARGS = -suppress 2583 -keep_delta
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VLOG_ARGS = -keep_delta
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#-------------------------------------------------
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# Bottom-of-Makefile
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#-------------------------------------------------
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# Include all simulator specific makefiles here
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# Each should define a unique target to simulate
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# e.g. xsim, vsim, etc and a common "clean" target
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include $(BASE_DIR)/../tools/make/viv_simulator.mak
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