61782b02d7
Co-authored-by: Andrew Moch <Andrew.Moch@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com> Co-authored-by: Joerg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Kumaran Subramoniam <kumaran.subramoniam@ni.com> Co-authored-by: Max Köhler <max.koehler@ni.com> Co-authored-by: Michael Auchter <michael.auchter@ni.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Co-authored-by: Hector Rubio <hrubio@ni.com> Original-commit: 6d3765605262016a80f71e36357f749ea35cbe5a
22 lines
632 B
Makefile
22 lines
632 B
Makefile
#
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# Copyright 2021 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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include $(TOOLS_DIR)/make/viv_ip_builder.mak
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IP_FIFO_4K_2CLK_SRCS = $(IP_BUILD_DIR)/fifo_4k_2clk/fifo_4k_2clk.xci
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IP_FIFO_4K_2CLK_HDL_SIM_SRCS = $(addprefix $(IP_BUILD_DIR)/fifo_4k_2clk/, \
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fifo_4k_2clk_sim_netlist.v \
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)
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IP_FIFO_4K_2CLK_OUTS = $(addprefix $(IP_BUILD_DIR)/fifo_4k_2clk/, \
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fifo_4k_2clk.xci.out \
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synth/fifo_4k_2clk.vhd \
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)
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$(IP_FIFO_4K_2CLK_SRCS) $(IP_FIFO_4K_2CLK_OUTS) : $(IP_DIR)/fifo_4k_2clk/fifo_4k_2clk.xci
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$(call BUILD_VIVADO_IP,fifo_4k_2clk,$(ARCH),$(PART_ID),$(IP_DIR),$(IP_BUILD_DIR),0)
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