michael-west
740202aa22
Added missing tuser connections. Signed-off-by: michael-west <michael.west@ettus.com> Original-commit: e3ffef975db464fb8d78f411c6fa0ad71f8e9b41
262 lines
9.4 KiB
Verilog
262 lines
9.4 KiB
Verilog
//
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// Copyright 2021 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: dds_freq_tune
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//
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// Description:
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//
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// Performs a frequency shift on a signal by multiplying it with a complex
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// sinusoid synthesized from a DDS. This module expects samples data to be in
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// {Q,I} order.
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//
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module dds_freq_tune #(
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parameter WIDTH = 24,
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parameter PHASE_WIDTH = 24,
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parameter SIN_COS_WIDTH = 16,
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parameter OUTPUT_WIDTH = 24
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) (
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input clk,
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input reset,
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input eob,
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input rate_changed,
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input [15:0] dds_input_fifo_occupied,
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// IQ input
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input [WIDTH*2-1:0] s_axis_din_tdata,
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input s_axis_din_tlast,
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input s_axis_din_tvalid,
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output s_axis_din_tready,
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// Phase input from NCO
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input [PHASE_WIDTH-1:0] s_axis_phase_tdata,
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input s_axis_phase_tlast,
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input s_axis_phase_tvalid,
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output s_axis_phase_tready,
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// IQ output
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output [OUTPUT_WIDTH*2-1:0] m_axis_dout_tdata,
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output m_axis_dout_tlast,
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output m_axis_dout_tvalid,
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input m_axis_dout_tready,
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// Debug signals
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output [ 2:0] state_out,
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output phase_valid_hold_out,
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output [ 7:0] phase_invalid_wait_count_out,
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output reset_dds_out,
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output m_axis_dds_tlast_out,
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output m_axis_dds_tvalid_out,
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output m_axis_dds_tready_out,
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output [SIN_COS_WIDTH*2-1:0] m_axis_dds_tdata_out
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);
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// Wires for DDS output
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wire m_axis_dds_tlast;
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wire m_axis_dds_tvalid;
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wire m_axis_dds_tready;
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wire [SIN_COS_WIDTH*2-1:0] m_axis_dds_tdata; // [31:16] = sin|q, [15:0]= cos|i
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reg reset_reg;
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reg phase_valid_hold;
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reg [7:0] phase_invalid_wait_count;
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reg [2:0] state;
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reg phase_ready_wait;
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wire s_axis_phase_tready_dds;
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// Initialize DDS resets to 1, since simulation model requires reset at time
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// 0 to avoid failure.
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reg reset_dds = 1'b1;
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reg reset_dds_reg = 1'b1;
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// When we're holding valid, make ready low so no new data comes in.
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assign s_axis_phase_tready = s_axis_phase_tready_dds & ~phase_valid_hold;
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localparam INIT = 3'b000;
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localparam VALID = 3'b001;
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localparam WAIT = 3'b010;
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localparam HOLD_VALID = 3'b011;
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// Reset needs to be 2 clk cycles minimum for Xilinx DDS IP
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always @(posedge clk) begin
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reset_reg <= reset;
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reset_dds_reg <= reset_dds;
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end
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// This state machine resets the DDS when data stops coming and also holds
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// valid high until the last packet has been flushed through the DDS.
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always @(posedge clk) begin
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if(reset) begin
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state <= INIT;
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phase_valid_hold <= 1'b0;
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phase_invalid_wait_count <= 16'h00;
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reset_dds <= 1'b0;
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end else begin
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case(state)
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INIT : begin
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phase_valid_hold <= 1'b0;
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phase_invalid_wait_count <= 16'h0000;
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reset_dds <= 1'b0;
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if(s_axis_phase_tvalid) begin
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state <= VALID;
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end
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end
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VALID : begin
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if(~s_axis_phase_tvalid) begin
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state <= WAIT;
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end
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end
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WAIT : begin
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// Wait until we either get valid data or don't.
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if(m_axis_dds_tready) begin
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// Only increment when the downstream can accept data.
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phase_invalid_wait_count <= phase_invalid_wait_count + 4'b1;
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end
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if(s_axis_phase_tvalid) begin
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// If we get valid data shortly after, then don't push data through
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// and reset.
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state <= INIT;
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end else begin
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if(eob | (phase_invalid_wait_count >= 16'h40) | rate_changed) begin
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// If a valid never comes (EOB)
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state <= HOLD_VALID;
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end
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end
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end
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HOLD_VALID : begin
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// Hold valid to flush data through the DDS. The DDS IP won't empty
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// without additional transfers.
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phase_valid_hold <= 1'b1;
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// Wait for input FIFO to be empty
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if (~s_axis_din_tvalid) begin
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state <= INIT;
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reset_dds <= 1'b1;
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end
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end
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endcase
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end
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end
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// DDS to generate sin/cos data from phase. It takes in a 24-bit phase value
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// and outputs two 16-bit values, with the sine value in the upper 16 bits
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// and the cosine value in the lower 16-bits.
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//
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// The phase input can be thought of as a 24-bit unsigned fixed-point value
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// with 24 fractional bits. In other words, the integer range of the input
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// maps to the the range [0, 2*pi) in radians.
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//
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// The output consists of two 16-bit signed fixed-point values with 14
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// fractional bits.
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//
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// This IP effectively computes Euler's formula, e^(j*2*pi*x) = cos(2*pi*x) +
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// j*sin(2*pi*x), where x is the phase value, and the output has the real
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// component in the lower bits and the imaginary component in the upper bits.
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dds_sin_cos_lut_only dds_sin_cos_lut_only_i (
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.aclk (clk),
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.aresetn (~(reset | reset_reg | reset_dds | reset_dds_reg)),
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.s_axis_phase_tvalid (s_axis_phase_tvalid | phase_valid_hold),
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.s_axis_phase_tready (s_axis_phase_tready_dds),
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.s_axis_phase_tlast (s_axis_phase_tlast),
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.s_axis_phase_tuser (1'b0),
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.s_axis_phase_tdata (s_axis_phase_tdata), // [23 : 0]
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.m_axis_data_tvalid (m_axis_dds_tvalid),
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.m_axis_data_tready (m_axis_dds_tready),
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.m_axis_data_tlast (m_axis_dds_tlast),
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.m_axis_data_tdata (m_axis_dds_tdata), // [31 : 0]
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.m_axis_data_tuser ()
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);
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wire [ WIDTH*2-1:0] mult_in_a_tdata;
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wire mult_in_a_tvalid;
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wire mult_in_a_tready;
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wire mult_in_a_tlast;
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wire [SIN_COS_WIDTH*2-1:0] mult_in_b_tdata;
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wire mult_in_b_tvalid;
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wire mult_in_b_tready;
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wire mult_in_b_tlast;
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wire [ 2*32-1:0] mult_out_tdata;
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wire mult_out_tvalid;
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wire mult_out_tready;
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wire mult_out_tlast;
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axi_sync #(
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.SIZE (2),
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.WIDTH_VEC ({SIN_COS_WIDTH*2, WIDTH*2}),
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.FIFO_SIZE (0)
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) axi_sync_i (
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.clk (clk),
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.reset (reset),
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.clear (),
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.i_tdata ({ m_axis_dds_tdata, s_axis_din_tdata }),
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.i_tlast ({ m_axis_dds_tlast, s_axis_din_tlast }),
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.i_tvalid ({ m_axis_dds_tvalid, s_axis_din_tvalid }),
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.i_tready ({ m_axis_dds_tready, s_axis_din_tready }),
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.o_tdata ({ mult_in_b_tdata, mult_in_a_tdata }),
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.o_tlast ({ mult_in_b_tlast, mult_in_a_tlast }),
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.o_tvalid ({ mult_in_b_tvalid, mult_in_a_tvalid }),
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.o_tready ({ mult_in_b_tready, mult_in_a_tready })
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);
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// Use a complex multiplier to multiply the input sample (A) by the NCO
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// output (B). This multiplier has a 21-bit input A, 16-bit input B, and
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// 32-bit output. Due to AXI-Stream requirements, A is rounded up to 24-bit.
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//
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// Assuming default parameters and unchanged IP, The A input (sample) is
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// 21-bit with 15 fractional bits, and the B input (NCO) is 16-bit with 14
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// fractional bits. The full result would be 21+16+1 = 38 bits, but the
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// output is configured for 32, dropping the lower 6 bits. Therefore, the
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// result has 15+14-6 = 23 fractional bits.
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//
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// a = Input IQ data stream as 48-bit, lower bits i, upper bits q.
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// b = Output of DDS as 32 bit cos/sin, lower bits cos, upper bits sin.
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complex_multiplier_dds complex_multiplier_dds_i (
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.aclk (clk),
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.aresetn (~(reset | reset_reg)),
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.s_axis_a_tvalid (mult_in_a_tvalid),
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.s_axis_a_tready (mult_in_a_tready),
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.s_axis_a_tlast (mult_in_a_tlast),
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.s_axis_a_tdata ({mult_in_a_tdata}), // [47 : 0]
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.s_axis_b_tvalid (mult_in_b_tvalid),
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.s_axis_b_tready (mult_in_b_tready),
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.s_axis_b_tlast (mult_in_b_tlast),
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.s_axis_b_tdata (mult_in_b_tdata), // [31 : 0]
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.m_axis_dout_tvalid (mult_out_tvalid),
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.m_axis_dout_tready (mult_out_tready),
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.m_axis_dout_tlast (mult_out_tlast),
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.m_axis_dout_tdata (mult_out_tdata) // [63 : 0]
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);
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// Round the 32-bit multiplier result down to 24 bits. This moves the binary
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// point so that we go from 23 fractional bits down to 15 fractional bits.
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axi_round_complex #(
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.WIDTH_IN (32),
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.WIDTH_OUT (OUTPUT_WIDTH)
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) axi_round_complex_i (
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.clk (clk),
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.reset (reset | reset_reg),
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.i_tdata (mult_out_tdata),
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.i_tlast (mult_out_tlast),
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.i_tvalid (mult_out_tvalid),
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.i_tready (mult_out_tready),
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.o_tdata (m_axis_dout_tdata),
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.o_tlast (m_axis_dout_tlast),
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.o_tvalid (m_axis_dout_tvalid),
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.o_tready (m_axis_dout_tready)
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);
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// Debug
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assign state_out = state;
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assign phase_valid_hold_out = phase_valid_hold;
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assign phase_invalid_wait_count_out = phase_invalid_wait_count;
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assign reset_dds_out = reset_dds;
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assign m_axis_dds_tlast_out = m_axis_dds_tlast;
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assign m_axis_dds_tvalid_out = m_axis_dds_tvalid;
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assign m_axis_dds_tready_out = m_axis_dds_tready;
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assign m_axis_dds_tdata_out = m_axis_dds_tdata;
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endmodule
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