Max Köhler
e9700b2081
So far only the implementation after opt_run is affected by the changes. Original-commit: 4c56b1b55ff3ae10561bd5efc83e3bb9a6a818d6
39 lines
1.4 KiB
Tcl
39 lines
1.4 KiB
Tcl
#
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# Copyright 2021 Ettus Research, a National Instruments Brand
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#
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# SPDX-License-Identifier: LGPL-3.0-or-later
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#
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source $::env(VIV_TOOLS_DIR)/scripts/viv_utils.tcl
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source $::env(VIV_TOOLS_DIR)/scripts/viv_strategies.tcl
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# STEP#1: Create project, add sources, refresh IP
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vivado_utils::initialize_project
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# STEP#2: Run synthesis
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vivado_utils::synthesize_design
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vivado_utils::generate_post_synth_reports
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# STEP#3: Run implementation strategy
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set strategy [vivado_strategies::get_impl_preset "Performance_ExplorePostRoutePhysOpt"]
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# Enable incremental build
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dict set strategy "implementation.incremental" $::env(VIV_INCR_BUILD)
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# Turn up uncertainty on 100Gb clocks(-quiet so if it fails because the clocks don't exist, it won't error)
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set_clock_uncertainty 0.5 -quiet -setup [get_clocks txoutclk_out*]
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# Vivado has been underestimating routing delays.
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dict set strategy "place_design.directive" "ExtraNetDelay_high"
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# Turn down uncertainty on 100Gb clocks
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dict set strategy "route_design.pre_hook" {set_clock_uncertainty 0.0 -quiet -setup [get_clocks txoutclk_out*]}
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vivado_strategies::implement_design $strategy
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# STEP#4: Generate reports
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vivado_utils::generate_post_route_reports
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# STEP#5: Generate a bitstream, netlist and debug probes
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set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [get_designs *]
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set byte_swap_bin 1
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vivado_utils::write_implementation_outputs $byte_swap_bin
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# Cleanup
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vivado_utils::close_batch_project
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