Use the real axi_fifo_2clk hierarchy with XPM-based asynchronous FIFO implementations instead of synthesizing axi_fifo_2clk_sim. Map the deep stream FIFOs into dedicated block RAM while preserving the legacy FWFT FIFO interface.
Kintex-7 B210 Vivado build
This directory recreates the clone's Vivado project from the canonical source
files stored in Git. The generated .xpr, .srcs, .runs, .gen, IP output
products, reports, and bitstreams live under build/ and are disposable.
Historical baseline
At the clone-vivado-2024.1 point in history, sources.tcl intentionally
matches the original Vivado 2024.1 project source set exactly. In particular it
contains:
lib/sim/fifo/axi_fifo_2clk_sim.v
as a synthesis source because that is what the original clone project used. Do not "clean up" that line in the historical baseline commit. The FIFO repair should be a later Git commit that replaces it with the hardware FIFO/XPM implementation, making the bug and fix visible in history.
Files
project_config.tcl-- part, top, expected Vivado version, default jobs.sources.tcl-- explicit source manifest; no recursive globs.create_project.tcl-- creates a disposable Project-Mode Vivado project.build.tcl-- full OOC-IP/synthesis/implementation/bitstream build.reports.tcl-- timing, route, bus-skew, CDC, methodology, utilization, power, and operating-condition reports.ip/b200_clk_gen/b200_clk_gen.xci-- version-controlled clock-wizard customization. It is imported into the generated project so the canonical XCI is never modified by a build.
Check the manifest
Before starting Vivado:
cd vivado/b210_k7
make check
For the reconstructed 2024.1 baseline this should report 99 entries and zero missing files. The count is expected to change in later commits when the FIFO/XPM sources are added.
Build
For the historical baseline, use Vivado 2024.1:
cd vivado/b210_k7
make build JOBS=8
Equivalent direct command:
B210_JOBS=8 vivado -mode batch -source vivado/b210_k7/build.tcl
Build products are written to:
build/images/usrp_b210_fpga.bit
build/images/usrp_b210_fpga.bin
build/reports/*.rpt
build/vivado/B210_Project_Firmwire/...
The .bin file is the raw image suitable for UHD's usrp_b210_fpga.bin.
Intentional Vivado migration
project_config.tcl rejects a different Vivado version by default. During an
explicit migration you can temporarily run:
B210_ALLOW_VIVADO_MISMATCH=1 vivado -mode batch -source vivado/b210_k7/create_project.tcl
Once the migration is validated, change B210_EXPECTED_VIVADO in
project_config.tcl in the migration commit (for example from 2024.1 to
2026.1).
Source-control rule
Edit files under lib/, top/, and vivado/b210_k7/. Never edit a copy under
build/. If deleting build/ prevents a clean rebuild from a fresh checkout,
then a required source is missing from Git or from sources.tcl.