5cadf901c7
Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Wade Fife <wade.fife@ni.com> Co-authored-by: Ryan Marlow <ryan@lmarlow.com> Original-commit: 596760a12e4834e47589c12f8a4fd083aa2f7c25
110 lines
3.1 KiB
Systemverilog
110 lines
3.1 KiB
Systemverilog
//
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// Copyright 2022 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: tb_adc_iq_repacker
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//
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// Description:
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//
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// This testbench mainly tests tb_adc_iq_repacker. It runs
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// 3 different tests:
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// - test data propagation when not swapping data
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// - test data propagation when swapping data
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// - check that data valid does not propagate when block
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// is not enabled.
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//
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`timescale 1ns/1ps
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`define NS_PER_TICK 1
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`define NUM_TEST_CASES 3
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`include "sim_clks_rsts.vh"
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`include "sim_exec_report.vh"
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module tb_adc_iq_repacker();
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import PkgRandom::*;
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`TEST_BENCH_INIT("tb_adc_iq_repacker", `NUM_TEST_CASES, `NS_PER_TICK);
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//sets up clock
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localparam CLK_PERIOD = $ceil(1e9/100.0e6);
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`DEFINE_CLK(clk, CLK_PERIOD, 50);
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//declare parameters
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localparam SPC = 1;
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localparam SAMPLE_WIDTH = 16;
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//declare wires and regs
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reg enable;
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reg valid_in;
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reg swap_iq;
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reg [SPC*SAMPLE_WIDTH-1:0] adc_q_in;
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reg [SPC*SAMPLE_WIDTH-1:0] adc_i_in;
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reg StopSim;
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wire [SPC*SAMPLE_WIDTH*2-1:0] data_out_tdata;
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wire data_out_tvalid;
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PkgRandom::Rand #(SPC*SAMPLE_WIDTH) rand_i;
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PkgRandom::Rand #(SPC*SAMPLE_WIDTH) rand_q;
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// instance adc_iq_repacker
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adc_iq_repacker #(
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.SPC(SPC),
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.SAMPLE_WIDTH(SAMPLE_WIDTH)
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) adc_iq_repacker_inst (
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.clk(clk),
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// Data in
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.adc_q_in(adc_q_in),
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.adc_i_in(adc_i_in),
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.valid_in(valid_in),
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.enable(enable),
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// Data is packed [Q,I] (I in LSBs) when swap_iq is '0', and [I,Q] otherwise
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.swap_iq(swap_iq),
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// Data out
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.data_out_tdata(data_out_tdata),
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.data_out_tvalid(data_out_tvalid)
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);
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// initial statement with test cases
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initial begin : tb_main
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// test data propagation when not swapping data
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`TEST_CASE_START("test data propagation, no swap, core enabled");
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repeat (10) @(posedge clk);
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swap_iq = 0;
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enable = 1;
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StopSim = 0;
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valid_in = 1;
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for (int i = 0; i < 10; i++) begin
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adc_q_in = rand_q.rand_bit();
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adc_i_in = rand_i.rand_bit();
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repeat (3) @(posedge clk);
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`ASSERT_ERROR(data_out_tdata[SAMPLE_WIDTH*2-1:0] == {adc_q_in[SAMPLE_WIDTH-1:0], adc_i_in[SAMPLE_WIDTH-1:0]}, "Output data is wrong");
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`ASSERT_ERROR(data_out_tvalid == 1, "output valid not asserted");
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end
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`TEST_CASE_DONE(1);
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// test data propagation when swapping data
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`TEST_CASE_START("test data propagation w/ swap_iq=1");
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swap_iq = 1;
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for (int i = 0; i < 10; i++) begin
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adc_q_in = rand_q.rand_bit();
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adc_i_in = rand_i.rand_bit();
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repeat (3) @(posedge clk);
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`ASSERT_ERROR(data_out_tdata[SAMPLE_WIDTH*2-1:0] == {adc_i_in[SAMPLE_WIDTH-1:0], adc_q_in[SAMPLE_WIDTH-1:0]}, "Output data is wrong");
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`ASSERT_ERROR(data_out_tvalid == 1, "output valid not asserted");
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end
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`TEST_CASE_DONE(1);
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// check that data valid does not propagate when block
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// is not enabled.
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`TEST_CASE_START("test data valid when enable = 0");
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enable = 0;
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repeat (10) @(posedge clk);
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`ASSERT_ERROR(data_out_tvalid == 0, "block should be disabled");
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`TEST_CASE_DONE(1);
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StopSim = 1;
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end
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endmodule : tb_adc_iq_repacker
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