61782b02d7
Co-authored-by: Andrew Moch <Andrew.Moch@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Javier Valenzuela <javier.valenzuela@ni.com> Co-authored-by: Joerg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Kumaran Subramoniam <kumaran.subramoniam@ni.com> Co-authored-by: Max Köhler <max.koehler@ni.com> Co-authored-by: Michael Auchter <michael.auchter@ni.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Co-authored-by: Hector Rubio <hrubio@ni.com> Original-commit: 6d3765605262016a80f71e36357f749ea35cbe5a
100 lines
3.6 KiB
VHDL
100 lines
3.6 KiB
VHDL
--
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-- Copyright 2021 Ettus Research, a National Instruments Brand
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--
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-- SPDX-License-Identifier: LGPL-3.0-or-later
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--
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-- Module: dac_gearbox_6x8
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--
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-- Description:
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--
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-- Gearbox to expand the data width from 6 SPC to 8 SPC.
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-- Input Clocks, all aligned to one another and coming from same MMCM
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-- PLL reference clock = 61.44 or 62.5 MHz.
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-- RfClk: 184.32 or 187.5 MHz (3x PLL reference clock)
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-- Clk1x: 122.88 or 125 MHz (2x PLL reference clock)
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-- Clk2x: 245.76 or 250 MHz (4x PLL reference clock)
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--
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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entity dac_gearbox_6x8 is
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port(
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Clk1x : in std_logic;
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Clk2x : in std_logic;
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RfClk : in std_logic;
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ac1Reset_n : in std_logic;
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ac2Reset_n : in std_logic;
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arReset_n : in std_logic;
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-- 16 bit data packing: [Q5,I5,Q4,I4,Q3,I3,Q2,I2,Q1,I1,Q0,I0] (I in LSBs)
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c2DataIn : in std_logic_vector(191 downto 0);
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c2DataValidIn : in std_logic;
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-- 16 bit data packing: [Q7,I7,Q6,I6,..,Q2,I2,Q1,I1,Q0,I0] (I in LSBs)
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rDataOut : out std_logic_vector(255 downto 0) := (others => '0');
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rReadyForOutput : in std_logic;
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rDataValidOut : out std_logic := '0'
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);
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end dac_gearbox_6x8;
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architecture struct of dac_gearbox_6x8 is
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signal c1DataOut : std_logic_vector(383 downto 0);
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signal c1DataValidOut : std_logic;
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begin
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-- Clk1x, Clk2x, and RfClk are source from the same PLL and have a known
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-- phase relationship between power cycles. Since, they have known phase
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-- relationship, clock crossing as be done without a dual clock FIFO or any
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-- other handshaking mechanism. We cannot move data from Clk2x to RfClk
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-- because of the clock relation between these two clocks will make it almost
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-- impossible to close timing. So, we move data from Clk2x to Clk1x and then
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-- to RfClk domain. Since, we need deterministic delay in the data path, we
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-- cannot use a FIFO to do data crossing.
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--
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-- Clk1x = Sample clock/24
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-- Clk2x = Sample clock/12
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-- RfClk = Sample clock/16
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--
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-- Clk1x __/-----\_____/-----\_____/-----\_____/-----\_____/-----\___
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-- | |
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-- Clk2x __/--\__/--\__/--\__/--\__/--\ | |
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-- | | | |
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-- | | <- Setup relationship | | <- Setup relationship
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-- | | | |
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-- RfClk __/---\___/---\___/---\___/---\___/---\___/---\___/---\___/-
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--
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-- As you can see the setup relationship for passing data synchronously from
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-- Clk2x to RfClk is very small (Sample clock period * 4). It is not possible
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-- to close timing with this requirement. For passing data from Clk1x to
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-- RfClk the setup relationship is (Sample clock period * 8) which is
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-- relatively easy to close timing.
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dac_gearbox_6x12_i: entity work.dac_gearbox_6x12 (RTL)
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port map (
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Clk1x => Clk1x,
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Clk2x => Clk2x,
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ac1Reset_n => ac1Reset_n,
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ac2Reset_n => ac2Reset_n,
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c2DataIn => c2DataIn,
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c2DataValidIn => c2DataValidIn,
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c1DataOut => c1DataOut,
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c1DataValidOut => c1DataValidOut
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);
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dac_gearbox_12x8_i: entity work.dac_gearbox_12x8 (RTL)
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port map (
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Clk1x => Clk1x,
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RfClk => RfClk,
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ac1Reset_n => ac1Reset_n,
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arReset_n => arReset_n,
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c1DataIn => c1DataOut,
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c1DataValidIn => c1DataValidOut,
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rDataOut => rDataOut,
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rReadyForOutput => rReadyForOutput,
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rDataValidOut => rDataValidOut
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);
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end struct;
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