adf6f576c6
FPGA: - Split up MB registers that control daughterboard specific settings so that daughterboards 0 and 1 could have different setings, in preparation for future devices that require different settings. This requires a compat number bump to 8.0. - Add registers for additional RFDC information, including the block/tile mapping of the individual channels, and information about resampling capabilities - Identify sections of code that would be specific to X410/ZBX and move them to their own headers, so it's trivial to add device-specific sections of code instead for other devices in the future. - This includes constraints for clocks and I/O pins. - Remove ability to do timed ctrlport transactions to the MB CPLD, this was unused and possibly broken. - Move daughterboard-specific code into its own code location (dboards/zbx) - Move X410-specific register documentation to its own location (doc/X410) - Refactor Makefiles to split out X410/ZBX specific components and allow switching between device types - Add 512-bit AXI interconnects - Make number of timekeepers configurable (X410 keeps the single timekeeper) MPM: - Required compat is bumped to 8.0 - Now supports new registers for detecting DSP capabilities and multi-rate settings for the daughterboards - Adds MMCM controls (currently unused) Co-authored-by: Wade Fife <wade.fife@ni.com> Co-authored-by: Ryan Marlow <ryan@lmarlow.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Original-commit: c1d268917ea65dd9c5a42366014cb96d3c025223
72 lines
3.7 KiB
Systemverilog
72 lines
3.7 KiB
Systemverilog
//
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// Copyright 2023 Ettus Research, A National Instruments Company
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: cpld_interface_regmap_utils.vh
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// Description:
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// The constants in this file are autogenerated by XmlParse.
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//===============================================================================
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// A numerically ordered list of registers and their HDL source files
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//===============================================================================
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// SIGNATURE_REGISTER : 0x0 (cpld_interface_regs.v)
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// SCRATCH_REGISTER : 0xC (cpld_interface_regs.v)
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// IPASS_CONTROL : 0x10 (cpld_interface_regs.v)
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// MOTHERBOARD_CPLD_DIVIDER : 0x20 (cpld_interface_regs.v)
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// DAUGHTERBOARD_CPLD_DIVIDER : 0x24 (cpld_interface_regs.v)
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//===============================================================================
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// RegTypes
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//===============================================================================
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//===============================================================================
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// Register Group CPLD_INTERFACE_REGS
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//===============================================================================
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// SIGNATURE_REGISTER Register (from cpld_interface_regs.v)
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localparam SIGNATURE_REGISTER = 'h0; // Register Offset
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localparam SIGNATURE_REGISTER_SIZE = 32; // register width in bits
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localparam SIGNATURE_REGISTER_MASK = 32'hFFFFFFFF;
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localparam PRODUCT_SIGNATURE_SIZE = 32; //SIGNATURE_REGISTER:PRODUCT_SIGNATURE
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localparam PRODUCT_SIGNATURE_MSB = 31; //SIGNATURE_REGISTER:PRODUCT_SIGNATURE
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localparam PRODUCT_SIGNATURE = 0; //SIGNATURE_REGISTER:PRODUCT_SIGNATURE
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// SCRATCH_REGISTER Register (from cpld_interface_regs.v)
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localparam SCRATCH_REGISTER = 'hC; // Register Offset
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localparam SCRATCH_REGISTER_SIZE = 32; // register width in bits
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localparam SCRATCH_REGISTER_MASK = 32'h0;
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//===============================================================================
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// Register Group CPLD_SPI_CONTROL_REGS
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//===============================================================================
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// MOTHERBOARD_CPLD_DIVIDER Register (from cpld_interface_regs.v)
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localparam MOTHERBOARD_CPLD_DIVIDER = 'h20; // Register Offset
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localparam MOTHERBOARD_CPLD_DIVIDER_SIZE = 32; // register width in bits
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localparam MOTHERBOARD_CPLD_DIVIDER_MASK = 32'hFFFF;
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localparam MB_DIVIDER_SIZE = 16; //MOTHERBOARD_CPLD_DIVIDER:MB_DIVIDER
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localparam MB_DIVIDER_MSB = 15; //MOTHERBOARD_CPLD_DIVIDER:MB_DIVIDER
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localparam MB_DIVIDER = 0; //MOTHERBOARD_CPLD_DIVIDER:MB_DIVIDER
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// DAUGHTERBOARD_CPLD_DIVIDER Register (from cpld_interface_regs.v)
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localparam DAUGHTERBOARD_CPLD_DIVIDER = 'h24; // Register Offset
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localparam DAUGHTERBOARD_CPLD_DIVIDER_SIZE = 32; // register width in bits
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localparam DAUGHTERBOARD_CPLD_DIVIDER_MASK = 32'hFFFF;
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localparam DB_DIVIDER_SIZE = 16; //DAUGHTERBOARD_CPLD_DIVIDER:DB_DIVIDER
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localparam DB_DIVIDER_MSB = 15; //DAUGHTERBOARD_CPLD_DIVIDER:DB_DIVIDER
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localparam DB_DIVIDER = 0; //DAUGHTERBOARD_CPLD_DIVIDER:DB_DIVIDER
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//===============================================================================
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// Register Group IPASS_REGS
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//===============================================================================
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// IPASS_CONTROL Register (from cpld_interface_regs.v)
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localparam IPASS_CONTROL = 'h10; // Register Offset
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localparam IPASS_CONTROL_SIZE = 32; // register width in bits
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localparam IPASS_CONTROL_MASK = 32'h1;
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localparam IPASS_ENABLE_TRANSFER_SIZE = 1; //IPASS_CONTROL:IPASS_ENABLE_TRANSFER
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localparam IPASS_ENABLE_TRANSFER_MSB = 0; //IPASS_CONTROL:IPASS_ENABLE_TRANSFER
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localparam IPASS_ENABLE_TRANSFER = 0; //IPASS_CONTROL:IPASS_ENABLE_TRANSFER
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