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Martin BraunAlex WilliamsAndrej RodeAshish ChaudhariBen HilburnCiro NishiguchiDaniel JepsonDerek KozelEJ KreinarHumberto JimenezIan BuckleyJörg HofrichterJon KiserJosh BlumJonathon PendlumMatt EttusMichael WestMoritz FischerNick FosterNicolas CuervoPaul ButlerPaul DavidRyan MarlowSugandha GuptaSylvain MunautTrung TranVidush VishwanathWade Fife
6b67702ad7
Martin BraunAlex WilliamsAndrej RodeAshish ChaudhariBen HilburnCiro NishiguchiDaniel JepsonDerek KozelEJ KreinarHumberto JimenezIan BuckleyJörg HofrichterJon KiserJosh BlumJonathon PendlumMatt EttusMichael WestMoritz FischerNick FosterNicolas CuervoPaul ButlerPaul DavidRyan MarlowSugandha GuptaSylvain MunautTrung TranVidush VishwanathWade FifeThe FPGA codebase was removed from the UHD repository in 2014 to reduce the size of the repository. However, over the last half-decade, the split between the repositories has proven more burdensome than it has been helpful. By merging the FPGA code back, it will be possible to create atomic commits that touch both FPGA and UHD codebases. Continuous integration testing is also simplified by merging the repositories, because it was previously difficult to automatically derive the correct UHD branch when testing a feature branch on the FPGA repository. This commit also updates the license files and paths therein. We are therefore merging the repositories again. Future development for FPGA code will happen in the same repository as the UHD host code and MPM code. == Original Codebase and Rebasing == The original FPGA repository will be hosted for the foreseeable future at its original local location: https://github.com/EttusResearch/fpga/ It can be used for bisecting, reference, and a more detailed history. The final commit from said repository to be merged here is 05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as v4.0.0.0-pre-uhd-merge. If you have changes in the FPGA repository that you want to rebase onto the UHD repository, simply run the following commands: - Create a directory to store patches (this should be an empty directory): mkdir ~/patches - Now make sure that your FPGA codebase is based on the same state as the code that was merged: cd src/fpga # Or wherever your FPGA code is stored git rebase v4.0.0.0-pre-uhd-merge Note: The rebase command may look slightly different depending on what exactly you're trying to rebase. - Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge: git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches Note: Make sure that only patches are stored in your output directory. It should otherwise be empty. Make sure that you picked the correct range of commits, and only commits you wanted to rebase were exported as patch files. - Go to the UHD repository and apply the patches: cd src/uhd # Or wherever your UHD repository is stored git am --directory fpga ~/patches/* rm -rf ~/patches # This is for cleanup == Contributors == The following people have contributed mainly to these files (this list is not complete): Co-authored-by: Alex Williams <alex.williams@ni.com> Co-authored-by: Andrej Rode <andrej.rode@ettus.com> Co-authored-by: Ashish Chaudhari <ashish@ettus.com> Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com> Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com> Co-authored-by: Daniel Jepson <daniel.jepson@ni.com> Co-authored-by: Derek Kozel <derek.kozel@ettus.com> Co-authored-by: EJ Kreinar <ej@he360.com> Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com> Co-authored-by: Ian Buckley <ian.buckley@gmail.com> Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com> Co-authored-by: Jon Kiser <jon.kiser@ni.com> Co-authored-by: Josh Blum <josh@joshknows.com> Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com> Co-authored-by: Martin Braun <martin.braun@ettus.com> Co-authored-by: Matt Ettus <matt@ettus.com> Co-authored-by: Michael West <michael.west@ettus.com> Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com> Co-authored-by: Nick Foster <nick@ettus.com> Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com> Co-authored-by: Paul Butler <paul.butler@ni.com> Co-authored-by: Paul David <paul.david@ettus.com> Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com> Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com> Co-authored-by: Sylvain Munaut <tnt@246tNt.com> Co-authored-by: Trung Tran <trung.tran@ettus.com> Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com> Co-authored-by: Wade Fife <wade.fife@ettus.com> Original-commit: bafa9d95453387814ef25e6b6256ba8db2df612f
103 lines
2.9 KiB
Plaintext
103 lines
2.9 KiB
Plaintext
##############################################################
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#
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# Xilinx Core Generator version 14.7
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# Date: Tue Jun 9 23:48:14 2015
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#
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##############################################################
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#
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# This file contains the customisation parameters for a
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# Xilinx CORE Generator IP GUI. It is strongly recommended
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# that you do not manually alter this file as it may cause
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# unexpected and unsupported behavior.
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#
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##############################################################
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#
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# Generated from component: xilinx.com:ip:fir_compiler:5.0
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#
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##############################################################
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#
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# BEGIN Project Options
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SET addpads = false
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SET asysymbol = true
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SET busformat = BusFormatAngleBracketNotRipped
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SET createndf = false
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SET designentry = Verilog
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SET device = xc6slx75
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SET devicefamily = spartan6
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SET flowvendor = Other
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SET formalverification = false
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SET foundationsym = false
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SET implementationfiletype = Ngc
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SET package = fgg484
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SET removerpms = false
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SET simulationfiles = Behavioral
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SET speedgrade = -3
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SET verilogsim = true
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SET vhdlsim = false
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# END Project Options
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# BEGIN Select
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SELECT FIR_Compiler family Xilinx,_Inc. 5.0
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# END Select
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# BEGIN Parameters
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CSET allow_rounding_approximation=false
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CSET bestprecision=false
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CSET chan_in_adv=0
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CSET clock_frequency=64
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CSET coefficient_buffer_type=Automatic
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CSET coefficient_file=./hb47.coe
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CSET coefficient_fractional_bits=0
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CSET coefficient_reload=true
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CSET coefficient_sets=1
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CSET coefficient_sign=Signed
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CSET coefficient_structure=Half_Band
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CSET coefficient_width=18
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CSET coefficientsource=COE_File
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CSET coefficientvector=6,0,-4,-3,5,6,-6,-13,7,44,64,44,7,-13,-6,6,5,-3,-4,0,6
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CSET columnconfig=4
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CSET component_name=hbdec2
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CSET data_buffer_type=Automatic
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CSET data_fractional_bits=0
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CSET data_sign=Signed
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CSET data_width=24
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CSET decimation_rate=2
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CSET displayreloadorder=false
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CSET filter_architecture=Systolic_Multiply_Accumulate
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CSET filter_selection=1
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CSET filter_type=Decimation
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CSET gui_behaviour=Coregen
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CSET hardwareoversamplingrate=1
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CSET has_ce=true
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CSET has_data_valid=true
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CSET has_nd=true
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CSET has_sclr=true
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CSET input_buffer_type=Automatic
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CSET inter_column_pipe_length=4
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CSET interpolation_rate=1
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CSET multi_column_support=Disabled
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CSET number_channels=1
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CSET number_paths=2
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CSET optimization_goal=Area
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CSET output_buffer_type=Automatic
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CSET output_rounding_mode=Full_Precision
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CSET output_width=47
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CSET passband_max=0.5
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CSET passband_min=0.0
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CSET preference_for_other_storage=Automatic
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CSET quantization=Integer_Coefficients
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CSET rate_change_type=Integer
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CSET ratespecification=Frequency_Specification
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CSET registered_output=true
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CSET sample_frequency=32
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CSET sampleperiod=1
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CSET sclr_deterministic=true
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CSET stopband_max=1.0
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CSET stopband_min=0.5
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CSET usechan_in_adv=false
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CSET zero_pack_factor=1
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# END Parameters
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# BEGIN Extra information
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MISC pkg_timestamp=2013-10-13T18:46:09Z
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# END Extra information
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GENERATE
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# CRC: 7b386b7e
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