111 lines
4.6 KiB
Systemverilog
111 lines
4.6 KiB
Systemverilog
//
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// Copyright 2025 Ettus Research, a National Instruments Brand
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: ctrlport_splitter
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//
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// Description:
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//
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// This block splits a single control port interface into multiple. It is used
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// when you have a single master that needs to access multiple slaves. For
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// example, a NoC block where the registers are implemented in multiple
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// submodules that must be read/written by a single NoC shell.
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//
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// Note that this block does not do any address decoding, so the connected
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// slaves must use non-overlapping address spaces.
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//
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// This module takes the request received by its single slave interface and
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// outputs it on all its master interfaces. In the opposite direction, it takes
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// the responses received by its multiple master interfaces and combines them
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// into a single response on its slave interface. This is done by using the ack
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// bit of each response to mask the other bits of the response, then OR'ing all
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// of the masked responses together onto a single response bus. This is valid
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// because only one block is allowed to respond to a single request.
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//
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// Parameters:
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//
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// NUM_SLAVES : The number of slaves you want to connect to a master.
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//
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module ctrlport_splitter
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import ctrlport_pkg::*;
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#(
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int NUM_SLAVES = 2
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) (
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input logic ctrlport_clk,
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input logic ctrlport_rst,
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// Slave Interface
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input logic s_ctrlport_req_wr,
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input logic s_ctrlport_req_rd,
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input logic [ CTRLPORT_ADDR_W-1:0] s_ctrlport_req_addr,
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input logic [ CTRLPORT_DATA_W-1:0] s_ctrlport_req_data,
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input logic [CTRLPORT_BYTE_EN_W-1:0] s_ctrlport_req_byte_en,
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input logic s_ctrlport_req_has_time,
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input logic [ CTRLPORT_TIME_W-1:0] s_ctrlport_req_time,
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output logic s_ctrlport_resp_ack,
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output logic [ CTRLPORT_STS_W-1:0] s_ctrlport_resp_status,
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output logic [ CTRLPORT_DATA_W-1:0] s_ctrlport_resp_data,
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// Master Interfaces
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output logic [ NUM_SLAVES-1:0] m_ctrlport_req_wr,
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output logic [ NUM_SLAVES-1:0] m_ctrlport_req_rd,
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output logic [ CTRLPORT_ADDR_W*NUM_SLAVES-1:0] m_ctrlport_req_addr,
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output logic [ CTRLPORT_DATA_W*NUM_SLAVES-1:0] m_ctrlport_req_data,
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output logic [CTRLPORT_BYTE_EN_W*NUM_SLAVES-1:0] m_ctrlport_req_byte_en,
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output logic [ NUM_SLAVES-1:0] m_ctrlport_req_has_time,
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output logic [ CTRLPORT_TIME_W*NUM_SLAVES-1:0] m_ctrlport_req_time,
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input logic [ NUM_SLAVES-1:0] m_ctrlport_resp_ack,
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input logic [ CTRLPORT_STS_W*NUM_SLAVES-1:0] m_ctrlport_resp_status,
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input logic [ CTRLPORT_DATA_W*NUM_SLAVES-1:0] m_ctrlport_resp_data
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);
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// Define interfaces
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ctrlport_if s_ctrlport_if(.clk(ctrlport_clk), .rst(ctrlport_rst));
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ctrlport_if m_ctrlport_if[NUM_SLAVES](.clk(ctrlport_clk), .rst(ctrlport_rst));
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// Map existing ports to ctrlport_if
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always_comb begin
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s_ctrlport_if.req = '0;
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s_ctrlport_if.req.wr = s_ctrlport_req_wr;
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s_ctrlport_if.req.rd = s_ctrlport_req_rd;
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s_ctrlport_if.req.addr = s_ctrlport_req_addr;
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s_ctrlport_if.req.data = s_ctrlport_req_data;
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s_ctrlport_if.req.byte_en = s_ctrlport_req_byte_en;
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s_ctrlport_if.req.has_time = s_ctrlport_req_has_time;
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s_ctrlport_if.req.timestamp = s_ctrlport_req_time;
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s_ctrlport_resp_ack = s_ctrlport_if.resp.ack;
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s_ctrlport_resp_status = s_ctrlport_if.resp.status;
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s_ctrlport_resp_data = s_ctrlport_if.resp.data;
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end
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// Instantiate ctrlport_if_splitter module
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ctrlport_if_splitter #(
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.NUM_SLAVES(NUM_SLAVES)
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) splitter_inst (
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.s_ctrlport(s_ctrlport_if),
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.m_ctrlport(m_ctrlport_if)
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);
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// Unpack ctrlport_if to output port
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for (genvar i = 0; i < NUM_SLAVES; i++) begin : output_gen
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always_comb begin
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m_ctrlport_req_wr[i] = m_ctrlport_if[i].req.wr;
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m_ctrlport_req_rd[i] = m_ctrlport_if[i].req.rd;
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m_ctrlport_req_addr[i*CTRLPORT_ADDR_W +: CTRLPORT_ADDR_W] = m_ctrlport_if[i].req.addr;
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m_ctrlport_req_data[i*CTRLPORT_DATA_W +: CTRLPORT_DATA_W] = m_ctrlport_if[i].req.data;
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m_ctrlport_req_byte_en[i*CTRLPORT_BYTE_EN_W +: CTRLPORT_BYTE_EN_W] = m_ctrlport_if[i].req.byte_en;
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m_ctrlport_req_has_time[i] = m_ctrlport_if[i].req.has_time;
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m_ctrlport_req_time[i*CTRLPORT_TIME_W +: CTRLPORT_TIME_W] = m_ctrlport_if[i].req.timestamp;
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m_ctrlport_if[i].resp.ack = m_ctrlport_resp_ack[i];
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m_ctrlport_if[i].resp.status = ctrlport_status_t'(m_ctrlport_resp_status[i*CTRLPORT_STS_W +: CTRLPORT_STS_W]);
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m_ctrlport_if[i].resp.data = m_ctrlport_resp_data[i*CTRLPORT_DATA_W +: CTRLPORT_DATA_W];
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end
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end
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endmodule
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