Ryan Volz
1451ae066b
A digital DC bias caused by various truncations in the DDC chain was previously noticable with small signal levels, especially with high decimation rates. This patch eliminates the bias by replacing the truncation with rounding or simply keeping more bits for longer where it makes sense. This is essentially a forward port of a similar prior fix to the usrp2 DDC chain: https://github.com/EttusResearch/fpga/pull/4. Signed-off-by: Ryan Volz <ryan.volz@gmail.com> Original-commit: a57c162a0d11ab82a83c911a94272ceb6f7ff70a
413 lines
16 KiB
Verilog
413 lines
16 KiB
Verilog
//
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// Copyright 2011-2013 Ettus Research LLC
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// Copyright 2018 Ettus Research, a National Instruments Company
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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//! The USRP digital down-conversion chain
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module ddc_chain
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#(
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parameter BASE = 0,
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parameter DSPNO = 0,
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parameter WIDTH = 24,
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parameter NEW_HB_DECIM = 0,
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parameter DEVICE = "SPARTAN6"
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)
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(input clk, input rst, input clr,
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input set_stb, input [7:0] set_addr, input [31:0] set_data,
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// From RX frontend
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input [WIDTH-1:0] rx_fe_i,
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input [WIDTH-1:0] rx_fe_q,
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// To RX control
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output [31:0] sample,
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input run,
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output strobe,
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output [31:0] debug
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);
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localparam cwidth = 25;
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localparam zwidth = 24;
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wire [31:0] phase_inc;
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reg [31:0] phase;
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wire [17:0] scale_factor;
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wire [cwidth-1:0] to_cordic_i, to_cordic_q;
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wire [cwidth-1:0] i_cordic, q_cordic;
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reg [WIDTH-1:0] i_cordic_pipe, q_cordic_pipe;
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wire [WIDTH-1:0] i_cic, q_cic;
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wire strobe_cic, strobe_hb1, strobe_hb2;
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wire enable_hb1, enable_hb2;
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wire [7:0] cic_decim_rate;
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reg [WIDTH-1:0] rx_fe_i_mux, rx_fe_q_mux;
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wire realmode;
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wire swap_iq;
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wire invert_i;
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wire invert_q;
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setting_reg #(.my_addr(BASE+0)) sr_0
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(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
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.in(set_data),.out(phase_inc),.changed());
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setting_reg #(.my_addr(BASE+1), .width(18)) sr_1
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(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
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.in(set_data),.out(scale_factor),.changed());
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setting_reg #(.my_addr(BASE+2), .width(10)) sr_2
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(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
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.in(set_data),.out({enable_hb1, enable_hb2, cic_decim_rate}),.changed());
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setting_reg #(.my_addr(BASE+3), .width(4)) sr_3
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(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
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.in(set_data),.out({invert_i,invert_q,realmode,swap_iq}),.changed());
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// MUX so we can do realmode signals on either input
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always @(posedge clk)
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if(swap_iq)
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begin
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rx_fe_i_mux <= invert_i ? ~rx_fe_q : rx_fe_q;
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rx_fe_q_mux <= realmode ? {WIDTH{1'b0}} : invert_q ? ~rx_fe_i : rx_fe_i;
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end
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else
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begin
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rx_fe_i_mux <= invert_i ? ~rx_fe_i : rx_fe_i;
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rx_fe_q_mux <= realmode ? {WIDTH{1'b0}} : invert_q ? ~rx_fe_q : rx_fe_q;
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end
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// NCO
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always @(posedge clk)
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if(rst)
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phase <= 0;
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else if(~run)
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phase <= 0;
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else
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phase <= phase + phase_inc;
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// CORDIC 24-bit I/O
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// (Algorithmic gain through CORDIC => 1.647 * 0.5 = 0.8235)
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// (Worst case gain through rotation => SQRT(2) = 1.4142)
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// Total worst case gain => 0.8235 * 1.4142 = 1.1646
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// So add an extra MSB bit for word growth.
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sign_extend #(.bits_in(WIDTH), .bits_out(cwidth)) sign_extend_cordic_i (.in(rx_fe_i_mux), .out(to_cordic_i));
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sign_extend #(.bits_in(WIDTH), .bits_out(cwidth)) sign_extend_cordic_q (.in(rx_fe_q_mux), .out(to_cordic_q));
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cordic_z24 #(.bitwidth(cwidth))
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cordic(.clock(clk), .reset(rst), .enable(run),
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.xi(to_cordic_i),. yi(to_cordic_q), .zi(phase[31:32-zwidth]),
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.xo(i_cordic),.yo(q_cordic),.zo() );
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always @(posedge clk) begin
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i_cordic_pipe[23:0] <= i_cordic[24:1];
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q_cordic_pipe[23:0] <= q_cordic[24:1];
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end
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// CIC decimator 24 bit I/O
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// Applies crude 1/(2^N) right shift gain compensation internally to prevent excesive downstream word growth.
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// Output gain is = algo_gain/(POW(2,CEIL(LOG2(algo_gain))) where algo_gain is = cic_decim_rate^4
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// Thus output gain is <= 1.0 and no word growth occurs.
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cic_strober cic_strober(.clock(clk),.reset(rst),.enable(run),.rate(cic_decim_rate),
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.strobe_fast(1'b1),.strobe_slow(strobe_cic) );
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cic_decim #(.bw(WIDTH))
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decim_i (.clock(clk),.reset(rst),.enable(run),
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.rate(cic_decim_rate),.strobe_in(1'b1),.strobe_out(strobe_cic),
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.signal_in(i_cordic_pipe),.signal_out(i_cic));
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cic_decim #(.bw(WIDTH))
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decim_q (.clock(clk),.reset(rst),.enable(run),
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.rate(cic_decim_rate),.strobe_in(1'b1),.strobe_out(strobe_cic),
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.signal_in(q_cordic_pipe),.signal_out(q_cic));
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//////////////////////////////////////////////////////////////////////////
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//
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// Conditional compilation of either:
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// 1) New X300 style decimation filters, or
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// 2) Traditional N210 style decimation filters.
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//
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//////////////////////////////////////////////////////////////////////////
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generate
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if (NEW_HB_DECIM == 1) begin: new_hb
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wire reload_go, reload_we1, reload_we2, reload_ld1, reload_ld2;
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wire [17:0] coef_din;
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setting_reg #(.my_addr(BASE+4), .width(22)) sr_4
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(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
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.in(set_data),.out({reload_ld2,reload_we2,reload_ld1,reload_we1,coef_din[17:0]}),.changed(reload_go));
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// Halfbands
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wire nd1, nd2, nd3;
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wire rfd1, rfd2, rfd3;
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wire rdy1, rdy2, rdy3;
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wire data_valid1, data_valid2, data_valid3;
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wire [46:0] i_hb1, q_hb1;
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wire [46:0] i_hb2, q_hb2;
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localparam HB1_SCALE = 18;
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localparam HB2_SCALE = 18;
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assign strobe_hb1 = data_valid1;
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assign strobe_hb2 = data_valid2;
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assign nd1 = strobe_cic;
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assign nd2 = strobe_hb1;
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// Default Coeffs have gain of ~1.0
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hbdec1 hbdec1
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(.clk(clk), // input clk
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.sclr(rst), // input sclr
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.ce(enable_hb1), // input ce
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.coef_ld(reload_go & reload_ld1), // input coef_ld
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.coef_we(reload_go & reload_we1), // input coef_we
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.coef_din(coef_din), // input [17 : 0] coef_din
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.rfd(rfd1), // output rfd
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.nd(nd1), // input nd
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.din_1(i_cic), // input [23 : 0] din_1
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.din_2(q_cic), // input [23 : 0] din_2
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.rdy(rdy1), // output rdy
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.data_valid(data_valid1), // output data_valid
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.dout_1(i_hb1), // output [46 : 0] dout_1
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.dout_2(q_hb1)); // output [46 : 0] dout_2
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// Default Coeffs have gain of ~1.0
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hbdec2 hbdec2
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(.clk(clk), // input clk
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.sclr(rst), // input sclr
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.ce(enable_hb2), // input ce
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.coef_ld(reload_go & reload_ld2), // input coef_ld
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.coef_we(reload_go & reload_we2), // input coef_we
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.coef_din(coef_din), // input [17 : 0] coef_din
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.rfd(rfd2), // output rfd
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.nd(nd2), // input nd
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.din_1(i_hb1[WIDTH-1+HB1_SCALE:HB1_SCALE]), // input [23 : 0] din_1
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.din_2(q_hb1[WIDTH-1+HB1_SCALE:HB1_SCALE]), // input [23 : 0] din_2
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.rdy(rdy2), // output rdy
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.data_valid(data_valid2), // output data_valid
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.dout_1(i_hb2), // output [46 : 0] dout_1
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.dout_2(q_hb2)); // output [46 : 0] dout_2
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reg [WIDTH-1:0] i_unscaled, q_unscaled;
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reg strobe_unscaled;
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always @(posedge clk)
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case({enable_hb1,enable_hb2})
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// No Halfbands enabled, no decimation.
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2'd0 :
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begin
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strobe_unscaled <= strobe_cic;
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i_unscaled <= i_cic;
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q_unscaled <= q_cic;
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end
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// ILLEGAL. Only half sample rate half band enabled.
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2'd1 :
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begin
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strobe_unscaled <= strobe_cic;
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i_unscaled <= i_cic;
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q_unscaled <= q_cic;
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end
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// One Halfband enabled, decimate by 2.
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2'd2 :
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begin
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strobe_unscaled <= strobe_hb1;
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i_unscaled <= i_hb1[WIDTH-1+HB1_SCALE:HB1_SCALE];
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q_unscaled <= q_hb1[WIDTH-1+HB1_SCALE:HB1_SCALE];
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end
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// Both Halfbands enabled, decimate by 4.
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2'd3 :
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begin
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strobe_unscaled <= strobe_hb2;
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i_unscaled <= i_hb2[WIDTH-1+HB2_SCALE:HB2_SCALE];
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q_unscaled <= q_hb2[WIDTH-1+HB2_SCALE:HB2_SCALE];
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end
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endcase // case (hb_rate)
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// round to 19 bits for clip (->18) followed by multiplication (total gain of 6 bits)
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wire [18:0] i_unscaled_rnd, q_unscaled_rnd;
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round #(
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.bits_in(WIDTH),
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.bits_out(19)
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) unscaled_rnd_i (
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.in(i_unscaled),
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.out(i_unscaled_rnd)
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);
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round #(
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.bits_in(WIDTH),
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.bits_out(19)
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) unscaled_rnd_q (
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.in(q_unscaled),
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.out(q_unscaled_rnd)
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);
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// Need to clip 1 bit here or we lose small signal performance out the
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// truncated LSB's for worst case CIC gain cases.
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// NOTE: We can only clip here with CORDIC rotating, CIC in it's highest gain configurations and an input signal thats
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// saturated.
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wire strobe_unscaled_clip;
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wire [17:0] i_unscaled_clip, q_unscaled_clip;
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clip_reg #(.bits_in(19), .bits_out(18), .STROBED(1)) unscaled_clip_i
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(.clk(clk), .in(i_unscaled_rnd), .strobe_in(strobe_unscaled), .out(i_unscaled_clip[17:0]), .strobe_out(strobe_unscaled_clip));
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clip_reg #(.bits_in(19), .bits_out(18), .STROBED(1)) unscaled_clip_q
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(.clk(clk), .in(q_unscaled_rnd), .strobe_in(strobe_unscaled), .out(q_unscaled_clip[17:0]), .strobe_out());
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// Apply scaling gain to compensate for CORDIC and CIC gain adjustments so that signal swing over network transport has
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// optimal dynamic range.
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wire [35:0] prod_i, prod_q;
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MULT_MACRO #(.DEVICE(DEVICE), // Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6","7SERIES"
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.LATENCY(1), // Desired clock cycle latency, 0-4
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.WIDTH_A(18), // Multiplier A-input bus width, 1-25
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.WIDTH_B(18)) // Multiplier B-input bus width, 1-18
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mult_i (.P(prod_i), // Multiplier output bus, width determined by WIDTH_P parameter
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.A(i_unscaled_clip), // Multiplier input A bus, width determined by WIDTH_A parameter
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.B(scale_factor), // Multiplier input B bus, width determined by WIDTH_B parameter
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.CE(strobe_unscaled_clip), // 1-bit active high input clock enable
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.CLK(clk), // 1-bit positive edge clock input
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.RST(rst)); // 1-bit input active high reset
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MULT_MACRO #(.DEVICE(DEVICE), // Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6","7SERIES"
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.LATENCY(1), // Desired clock cycle latency, 0-4
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.WIDTH_A(18), // Multiplier A-input bus width, 1-25
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.WIDTH_B(18)) // Multiplier B-input bus width, 1-18
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mult_q (.P(prod_q), // Multiplier output bus, width determined by WIDTH_P parameter
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.A(q_unscaled_clip), // Multiplier input A bus, width determined by WIDTH_A parameter
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.B(scale_factor), // Multiplier input B bus, width determined by WIDTH_B parameter
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.CE(strobe_unscaled_clip), // 1-bit active high input clock enable
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.CLK(clk), // 1-bit positive edge clock input
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.RST(rst)); // 1-bit input active high reset
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reg strobe_scaled;
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wire strobe_clip;
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wire [32:0] i_clip, q_clip;
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always @(posedge clk) strobe_scaled <= strobe_unscaled_clip;
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clip_reg #(.bits_in(36), .bits_out(33), .STROBED(1)) clip_i
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(.clk(clk), .in(prod_i[35:0]), .strobe_in(strobe_scaled), .out(i_clip), .strobe_out(strobe_clip));
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clip_reg #(.bits_in(36), .bits_out(33), .STROBED(1)) clip_q
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(.clk(clk), .in(prod_q[35:0]), .strobe_in(strobe_scaled), .out(q_clip), .strobe_out());
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round_sd #(.WIDTH_IN(33), .WIDTH_OUT(16)) round_i
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(.clk(clk), .reset(rst), .in(i_clip), .strobe_in(strobe_clip), .out(sample[31:16]), .strobe_out(strobe));
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round_sd #(.WIDTH_IN(33), .WIDTH_OUT(16)) round_q
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(.clk(clk), .reset(rst), .in(q_clip), .strobe_in(strobe_clip), .out(sample[15:0]), .strobe_out());
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end else begin: old_hb // block: new_hb
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///////////////////////////////////////////////
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//
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// Legacy Decimation Filters from USRP2
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//
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///////////////////////////////////////////////
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wire [WIDTH-1:0] i_hb1, q_hb1;
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wire [WIDTH-1:0] i_hb2, q_hb2;
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// First (small) halfband 24 bit I/O
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small_hb_dec #(.WIDTH(WIDTH),.DEVICE(DEVICE)) small_hb_i
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(.clk(clk),.rst(rst),.bypass(~enable_hb1),.run(run),
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.stb_in(strobe_cic),.data_in(i_cic),.stb_out(strobe_hb1),.data_out(i_hb1));
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small_hb_dec #(.WIDTH(WIDTH),.DEVICE(DEVICE)) small_hb_q
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(.clk(clk),.rst(rst),.bypass(~enable_hb1),.run(run),
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.stb_in(strobe_cic),.data_in(q_cic),.stb_out(),.data_out(q_hb1));
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// Second (large) halfband 24 bit I/O
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wire [8:0] cpi_hb = enable_hb1 ? {cic_decim_rate,1'b0} : {1'b0,cic_decim_rate};
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hb_dec #(.WIDTH(WIDTH),.DEVICE(DEVICE)) hb_i
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(.clk(clk),.rst(rst),.bypass(~enable_hb2),.run(run),.cpi(cpi_hb),
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.stb_in(strobe_hb1),.data_in(i_hb1),.stb_out(strobe_hb2),.data_out(i_hb2));
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hb_dec #(.WIDTH(WIDTH),.DEVICE(DEVICE)) hb_q
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(.clk(clk),.rst(rst),.bypass(~enable_hb2),.run(run),.cpi(cpi_hb),
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.stb_in(strobe_hb1),.data_in(q_hb1),.stb_out(),.data_out(q_hb2));
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// round to 19 bits for clip (->18) followed by multiplication (total gain of 6 bits)
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wire [18:0] i_hb_out_rnd, q_hb_out_rnd;
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round #(
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.bits_in(WIDTH),
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.bits_out(19)
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) hb_out_rnd_i (
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.in(i_hb2),
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.out(i_hb_out_rnd)
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);
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round #(
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.bits_in(WIDTH),
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.bits_out(19)
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) hb_out_rnd_q (
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.in(q_hb2),
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.out(q_hb_out_rnd)
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);
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// Need to clip 1 bit here or we loose small signal performance out the truncated LSB's for worst case CIC gain cases.
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wire strobe_unscaled_clip;
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wire [17:0] i_unscaled_clip, q_unscaled_clip;
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clip_reg #(.bits_in(19), .bits_out(18), .STROBED(1)) unscaled_clip_i
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(.clk(clk), .in(i_hb_out_rnd), .strobe_in(strobe_hb2), .out(i_unscaled_clip[17:0]), .strobe_out(strobe_unscaled_clip));
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clip_reg #(.bits_in(19), .bits_out(18), .STROBED(1)) unscaled_clip_q
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(.clk(clk), .in(q_hb_out_rnd), .strobe_in(strobe_hb2), .out(q_unscaled_clip[17:0]), .strobe_out());
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//scalar operation (gain of 6 bits)
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wire [35:0] prod_i, prod_q;
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MULT_MACRO #(.DEVICE(DEVICE), // Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6","7SERIES"
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.LATENCY(1), // Desired clock cycle latency, 0-4
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.WIDTH_A(18), // Multiplier A-input bus width, 1-25
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.WIDTH_B(18)) // Multiplier B-input bus width, 1-18
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mult_i (.P(prod_i), // Multiplier output bus, width determined by WIDTH_P parameter
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.A(i_unscaled_clip),// Multiplier input A bus, width determined by WIDTH_A parameter
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.B(scale_factor), // Multiplier input B bus, width determined by WIDTH_B parameter
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.CE(strobe_unscaled_clip), // 1-bit active high input clock enable
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.CLK(clk), // 1-bit positive edge clock input
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.RST(rst)); // 1-bit input active high reset
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MULT_MACRO #(.DEVICE(DEVICE), // Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6","7SERIES"
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.LATENCY(1), // Desired clock cycle latency, 0-4
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.WIDTH_A(18), // Multiplier A-input bus width, 1-25
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.WIDTH_B(18)) // Multiplier B-input bus width, 1-18
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mult_q (.P(prod_q), // Multiplier output bus, width determined by WIDTH_P parameter
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.A(q_unscaled_clip),// Multiplier input A bus, width determined by WIDTH_A parameter
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.B(scale_factor), // Multiplier input B bus, width determined by WIDTH_B parameter
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.CE(strobe_unscaled_clip), // 1-bit active high input clock enable
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.CLK(clk), // 1-bit positive edge clock input
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.RST(rst)); // 1-bit input active high reset
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reg strobe_scaled;
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wire strobe_clip;
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wire [32:0] i_clip, q_clip;
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always @(posedge clk) strobe_scaled <= strobe_unscaled_clip;
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clip_reg #(.bits_in(36), .bits_out(33), .STROBED(1)) clip_i
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(.clk(clk), .in(prod_i[35:0]), .strobe_in(strobe_scaled), .out(i_clip), .strobe_out(strobe_clip));
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clip_reg #(.bits_in(36), .bits_out(33), .STROBED(1)) clip_q
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(.clk(clk), .in(prod_q[35:0]), .strobe_in(strobe_scaled), .out(q_clip), .strobe_out());
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round_sd #(.WIDTH_IN(33), .WIDTH_OUT(16)) round_i
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(.clk(clk), .reset(rst), .in(i_clip), .strobe_in(strobe_clip), .out(sample[31:16]), .strobe_out(strobe));
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round_sd #(.WIDTH_IN(33), .WIDTH_OUT(16)) round_q
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(.clk(clk), .reset(rst), .in(q_clip), .strobe_in(strobe_clip), .out(sample[15:0]), .strobe_out());
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end // block: old_hb
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endgenerate
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assign debug = {enable_hb1, enable_hb2, run, strobe, strobe_cic, strobe_hb1, strobe_hb2};
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endmodule // ddc_chain
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