79 lines
2.2 KiB
Verilog
79 lines
2.2 KiB
Verilog
//
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// Copyright 2017 Ettus Research, a National Instruments Company
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//
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// SPDX-License-Identifier: LGPL-3.0-or-later
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//
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// Module: pulse_stretch
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//
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// Description:
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//
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// Pulse stretcher. Takes any input pulse that is SCALE+2 clock cycles or
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// less and outputs a pulse that is SCALE+1 clock cycles. However, if an
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// input pulse is longer than SCALE+2 clock cycles then the output pulse
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// repeats. If more than one pulse is input within SCALE+2 clock cycles then
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// additional pulses will be ignored.
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//
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// Examples (SCALE = 2):
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//
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// Clock _/‾\_/‾\_/‾\_/‾\_/‾\_/‾\_/‾\_/‾\_/‾\_/‾\_/‾\_/‾\_/‾\_/‾\_
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//
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//
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// pulse _/‾‾‾\_______________/‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾\___________________
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//
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// pulse_stretched _____/‾‾‾‾‾‾‾‾‾‾‾\_______/‾‾‾‾‾‾‾‾‾‾‾\___________________
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//
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//
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// pulse _/‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾‾\___________________________________
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//
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// pulse_stretched _____/‾‾‾‾‾‾‾‾‾‾‾\___/‾‾‾‾‾‾‾‾‾‾‾\_______________________
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//
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//
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// pulse _/‾‾‾\_______/‾‾‾\___/‾‾‾\_______/‾‾‾‾‾‾‾\_______________
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//
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// pulse_stretched _____/‾‾‾‾‾‾‾‾‾‾‾\_______/‾‾‾‾‾‾‾‾‾‾‾\___/‾‾‾‾‾‾‾‾‾‾‾\___
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// Parameters:
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//
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// SCALE : The number of clock cycles to add to a single cycle pulse. Or, the
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// number of clock cycles, minus 1, for the output pulse.
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//
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module pulse_stretch #(
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parameter SCALE = 64'd12_500_000
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)(
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input clk,
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input rst,
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input pulse,
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output pulse_stretched
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);
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reg [$clog2(SCALE+1)-1:0] count = 'd0;
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reg state = 1'b0;
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always @ (posedge clk)
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if (rst) begin
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state <= 1'b0;
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count <= 'd0;
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end
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else begin
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case (state)
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1'b0: begin
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if (pulse) begin
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state <= 1'b1;
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count <= 'd0;
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end
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end
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1'b1: begin
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count <= count + 1'b1;
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if (count == SCALE)
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state <= 1'b0;
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end
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endcase
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end
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assign pulse_stretched = (state == 1'b1);
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endmodule
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