Commit Graph
19 Commits
Author SHA1 Message Date
Wade Fife dd683cdee3 fpga: rfnoc: Add DEVICE_FAMILY to stream endpoint
Original-commit: 914a2b08f77a1725bf74a2cccf09b49f7506f53d
2023-02-13 10:50:45 -06:00
Wade Fife b26e5ed3a3 fpga: rfnoc: Add ULTRASCALE to chdr_ingress_fifo
Original-commit: a27d9e4fb92a895c0fe43b791e1d60838c8ad4c6
2023-02-13 10:50:45 -06:00
Wade Fife c2c8f03038 fpga: rfnoc: Add CHDR management util functions
Add missing chdr_mgmt_*() and enum_to_chdr_w() functions.


Original-commit: f6ec1496486f14ce16042062bdddcec38fa316a5
2021-11-04 11:04:54 -05:00
Wade Fife 1a72b843e8 fpga: rfnoc: Add labels to chdr_mgmt_pkt_handler
Original-commit: a8bb7d3ad98a77fb23e3695721b4bdd3768e6508
2021-10-28 23:15:41 -05:00
Wade Fife 40c76b8d9a fpga: rfnoc: Add ability to disable output flow control
Per the RFNoC specification, if we set the frequency of flow
control updates to 0 then the input stream will not send flow control
status updates to the output stream handler.

This change makes it so that when the frequency of flow control status
updates is configured to be zero in the FPGA output stream handler
(i.e., cfg_fc_freq_bytes and cfg_fc_freq_pkts are both 0 in
chdr_stream_output) then the output stream handler will not use flow
control. That is, chdr_stream_output will not expect stream status
updates and will not restrict output packets.


Original-commit: 184999c54f0f30a7952d4e8560b393730c00e353
2021-04-14 07:24:49 -05:00
Wade Fife cf524e9af5 fpga: rfnoc: Update CHDR stream INIT command
This changes the behavior of the stream command with the INIT OpCode
such that sending the command with 0 for the values causes no flow
control stream status packets to be sent in response to incoming data.


Original-commit: 7c849afec4dad605ff6f32f7319933f99a4cd1ce
2020-08-28 15:02:41 -05:00
Wade Fife 0c6f2627a5 fpga: lib: Fix lint warnings
Fixes various synthesis/simulation warnings that were being generated
due to incorrectly sized constants.


Original-commit: 00f683c91486647f1711eb4c0b0a917078d29652
2020-08-28 15:02:41 -05:00
Wade Fife 09461da1f5 fpga: rfnoc: Remove deprecated files
Original-commit: db0d2dddcc5d8e39e2b7843a326ad9392bbb4c3f
2020-08-23 13:52:26 -05:00
Wade Fife 845dfd4f87 fpga: lib: Add more CtrlPort constants
Add some missing CtrlPort signal widths to ctrlport.vh.


Original-commit: c9d55d870dbccbc07ca9a7afaf2e0ac64944111c
2020-08-19 12:28:22 -05:00
Wade Fife 8ed69c7cdb fpga: rfnoc: Fix clock crossing in axis_data_to_chdr
This fixes some incorrectly handled clock crossings from axis_data_clk
to axis_chdr_clk, which could have manifested as timing failures (on
E320) or incorrect behavior, depending on the product and noc_shell
configuration.

Also cleans up trailing white space.


Original-commit: f48af0a0876c99016eb8cd4558a31106bfc9baa1
2020-08-12 13:56:13 -05:00
Wade Fife 104a73e623 fpga: rfnoc: Add RFNoC Replay block
Original-commit: 6d92a1828121ca4b57d496bbf522820f961244b9
2020-08-04 15:40:08 -05:00
Wade Fife 59f5dcfc4f fpga: rfnoc: Add support for CHDR_W < ITEM_W*NIPC
This change fixes the case where CHDR_W < ITEM_W*NIPC.

It also adds a state machine to stall the input to the pyld_fifo to
ensure that the pkt_info_fifo will not overflow. Previously in some
cases it allowed the same word to be inserted into the pyld_fifo
multiple times.


Original-commit: b862eda69cf41c7044a1805324f2fcfef5b0ba3d
2020-08-04 15:40:08 -05:00
Andrew Moch 4313178af4 fpga: lib: Fix chdr_mgmt_pkt_handler when CHDR_W != 64
Original-commit: 3beb450e2ab29e6021f4091fd1a3cc6522f994c4
2020-07-30 15:28:35 -05:00
Wade Fife c3f45a92a0 fpga: rfnoc: Fix chdr_update_length function
Original-commit: 1cef9d62d698a7cc33f936ab3df32e6dcd933487
2020-06-29 14:03:17 -05:00
Andrew Moch 55881469ac fpga: rfnoc: Add support for 512-bit CHDR widths
This fixes the rfnoc_null_src_sink, chdr_crossbar_nxn, and
chdr_stream_endpoint blocks so that wider CHDR widths are properly
supported. It also updates PkgChdrBfm to able to properly test these
blocks. The testbenches have been updated to test both 64 and 512-bit
widths.


Original-commit: 3af8dcaacfa4bf36dcae3bdbf0b353385b7063c6
2020-06-18 09:09:34 -05:00
Wade Fife c33b3779f9 fpga: Change default MTU to 10
Original-commit: 7b7fa68880ca423ea3a47fc3dc97ba533921c9a5
2020-05-11 09:06:03 -05:00
Wade Fife 34d68cf4ca fpga: rfnoc: Add option to sample sideband info at start of packet
The axis_data_to_chdr block previously only sampled the sideband
information at the end of the packet. This adds a parameter that
controls if the sideband information should be sampled at the beginning
of the packet or the end of the packet. In the former case, large
internal packet buffers are not required.


Original-commit: a8c4f021277cf3b0a0897fa9da0252541512f3a6
2020-04-14 16:37:43 -05:00
Wade Fife c9c9543719 fpga: core: Add chdr_update_length function
Original-commit: 8c6eabcd86f8e5d1e25cfed441e1acf1a0b6759a
2020-04-14 16:37:43 -05:00
+18 6b67702ad7 Merge FPGA repository back into UHD repository
The FPGA codebase was removed from the UHD repository in 2014 to reduce
the size of the repository. However, over the last half-decade, the
split between the repositories has proven more burdensome than it has
been helpful. By merging the FPGA code back, it will be possible to
create atomic commits that touch both FPGA and UHD codebases. Continuous
integration testing is also simplified by merging the repositories,
because it was previously difficult to automatically derive the correct
UHD branch when testing a feature branch on the FPGA repository.

This commit also updates the license files and paths therein.

We are therefore merging the repositories again. Future development for
FPGA code will happen in the same repository as the UHD host code and
MPM code.

== Original Codebase and Rebasing ==

The original FPGA repository will be hosted for the foreseeable future
at its original local location: https://github.com/EttusResearch/fpga/

It can be used for bisecting, reference, and a more detailed history.

The final commit from said repository to be merged here is
05003794e2da61cabf64dd278c45685a7abad7ec. This commit is tagged as
v4.0.0.0-pre-uhd-merge.

If you have changes in the FPGA repository that you want to rebase onto
the UHD repository, simply run the following commands:

- Create a directory to store patches (this should be an empty
  directory):

    mkdir ~/patches

- Now make sure that your FPGA codebase is based on the same state as
  the code that was merged:

    cd src/fpga # Or wherever your FPGA code is stored
    git rebase v4.0.0.0-pre-uhd-merge

  Note: The rebase command may look slightly different depending on what
  exactly you're trying to rebase.

- Create a patch set for your changes versus v4.0.0.0-pre-uhd-merge:

    git format-patch v4.0.0.0-pre-uhd-merge -o ~/patches

  Note: Make sure that only patches are stored in your output directory.
  It should otherwise be empty. Make sure that you picked the correct
  range of commits, and only commits you wanted to rebase were exported
  as patch files.

- Go to the UHD repository and apply the patches:

    cd src/uhd # Or wherever your UHD repository is stored
    git am --directory fpga ~/patches/*
    rm -rf ~/patches # This is for cleanup

== Contributors ==

The following people have contributed mainly to these files (this list
is not complete):

Co-authored-by: Alex Williams <alex.williams@ni.com>
Co-authored-by: Andrej Rode <andrej.rode@ettus.com>
Co-authored-by: Ashish Chaudhari <ashish@ettus.com>
Co-authored-by: Ben Hilburn <ben.hilburn@ettus.com>
Co-authored-by: Ciro Nishiguchi <ciro.nishiguchi@ni.com>
Co-authored-by: Daniel Jepson <daniel.jepson@ni.com>
Co-authored-by: Derek Kozel <derek.kozel@ettus.com>
Co-authored-by: EJ Kreinar <ej@he360.com>
Co-authored-by: Humberto Jimenez <humberto.jimenez@ni.com>
Co-authored-by: Ian Buckley <ian.buckley@gmail.com>
Co-authored-by: Jörg Hofrichter <joerg.hofrichter@ni.com>
Co-authored-by: Jon Kiser <jon.kiser@ni.com>
Co-authored-by: Josh Blum <josh@joshknows.com>
Co-authored-by: Jonathon Pendlum <jonathan.pendlum@ettus.com>
Co-authored-by: Martin Braun <martin.braun@ettus.com>
Co-authored-by: Matt Ettus <matt@ettus.com>
Co-authored-by: Michael West <michael.west@ettus.com>
Co-authored-by: Moritz Fischer <moritz.fischer@ettus.com>
Co-authored-by: Nick Foster <nick@ettus.com>
Co-authored-by: Nicolas Cuervo <nicolas.cuervo@ettus.com>
Co-authored-by: Paul Butler <paul.butler@ni.com>
Co-authored-by: Paul David <paul.david@ettus.com>
Co-authored-by: Ryan Marlow <ryan.marlow@ettus.com>
Co-authored-by: Sugandha Gupta <sugandha.gupta@ettus.com>
Co-authored-by: Sylvain Munaut <tnt@246tNt.com>
Co-authored-by: Trung Tran <trung.tran@ettus.com>
Co-authored-by: Vidush Vishwanath <vidush.vishwanath@ettus.com>
Co-authored-by: Wade Fife <wade.fife@ettus.com>


Original-commit: bafa9d95453387814ef25e6b6256ba8db2df612f
2020-01-28 09:35:36 -08:00