2 Commits

Include renames

Author	SHA1	Message	Date
Wade Fife	feb849051f	fpga: lib: Add eth_ipv4_internal ... This adds a generic version of eth_internal that allows you to specify the CHDR width. Original-commit: 30b522b268aed6e7b4bc1a556e88d2a4b2fe6f77	2021-06-03 11:26:54 -05:00
Andrew Moch	05eb1bc2f1	fpga: lib: Add width agnostic version of Ethernet Interface ... The rnfoc/xport section is refactored in System Verilog to allow the following improvements (1) CPU_W - Sets the size of the c2e and e2c pipes. This can be run at a different clock rate than the main ethernet pipe (2) CHDR_W - Sets the size of the v2e and e2v pipes. This can be run at a different clock rate than the main ethernet pipe (3) ENET_W - Sets the size of the eth_tx and eth_rx pipes. eth_interface_tb runs traffic from e2c,e2v,v2e,c2e simultaneously against the original xport_sv implementation, and against the new implementation with widths of 64/128/512. A chdr_management node info request queries the port info of the node0 in the eth_interface. eth_ifc_synth_test.sv can be compiled with the make xsim target to test out the size of various configurations. Original-commit: eed4988cc266a63370a4332351d02fadedde3a3b	2020-06-30 10:29:35 -05:00