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e9a6fe4e2e6c2b520ab718bc4cda1b60b3a3d1eb
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Author SHA1 Message Date
Andrew Moch 8cb9bdd331 fpga: lib: Add AXI4 (full) interface 
Add a SystemVerilog interface for connecting AXI4 ports, and an
associated header file with helper macros.


Original-commit: 04d29e85b0c0698e3de96b54fd3f6e04eb439f74
 2021-06-03 11:26:54 -05:00