miegl/b210-k7-fpga
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a97634a2b3b61a30800a2ddaa6060f85228e28ab
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2 Commits
Author SHA1 Message Date
Wade Fife ab09eb9b09 fpga: lib: Add clock domain comments to interfaces 
Original-commit: c64258e09b221d0bfeb55e01085a20e37c5b62ba
 2021-06-03 11:26:54 -05:00
Andrew Moch 8cb9bdd331 fpga: lib: Add AXI4 (full) interface 
Add a SystemVerilog interface for connecting AXI4 ports, and an
associated header file with helper macros.


Original-commit: 04d29e85b0c0698e3de96b54fd3f6e04eb439f74
 2021-06-03 11:26:54 -05:00