3 Commits

Include renames

Author	SHA1	Message	Date
Martin Braun	8d0cc11269	ci: Update FPGA CI pipelines to match new image builder ... - Removes target names for X3x0 and X4x0 builds (these are now encoded in the YAML file) - Change the image core YAML file names referenced in the pipeline YAMLs to match the contents of fpga/usrp3/top/x?00/*.yml - Remove X410_XG_100 image since it is not a shipping image - Add image_core_name arguments for all E320, E31x, N3xx targets Original-commit: 50e07a5b42d4a244c12b5a13b51048573d0069ec	2024-06-11 10:20:08 +02:00
Martin Braun	e2c442ab8c	fpga: Update tooling to use image builder instead of make ... This modifies repeat_fpga_build.py such that it can take a YAML file as input, not just a make target. It will then use the image builder to prepare the build and generate a valid make command, which in turn is used to build FPGA images repeatedly. Original-commit: 09f3453f39363870f1c03ef1c917a0dedb7598df	2024-02-25 16:54:12 -06:00
Wade Fife	c525cba09c	fpga: tools: Add repeat_fpga_build.py ... This script allows you to repeatedly run an FPGA build until it successfully meets timing. Original-commit: f72e8daeecf7dff92dce47be0b956699b5e40a16	2023-02-07 23:04:12 -06:00